From: Baolu Lu <baolu.lu@linux.intel.com>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: baolu.lu@linux.intel.com, Joerg Roedel <joro@8bytes.org>,
Christoph Hellwig <hch@infradead.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Kevin Tian <kevin.tian@intel.com>,
Ashok Raj <ashok.raj@intel.com>, Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Jean-Philippe Brucker <jean-philippe@linaro.com>,
Dave Jiang <dave.jiang@intel.com>,
Fenghua Yu <fenghua.yu@intel.com>, Vinod Koul <vkoul@kernel.org>,
Eric Auger <eric.auger@redhat.com>, Liu Yi L <yi.l.liu@intel.com>,
Jacob jun Pan <jacob.jun.pan@intel.com>,
Zhangfei Gao <zhangfei.gao@linaro.org>,
Zhu Tony <tony.zhu@intel.com>,
iommu@lists.linux.dev, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org,
Jean-Philippe Brucker <jean-philippe@linaro.org>
Subject: Re: [PATCH v13 09/13] iommu/sva: Refactoring iommu_sva_bind/unbind_device()
Date: Fri, 23 Sep 2022 10:31:32 +0800 [thread overview]
Message-ID: <ca854564-f231-1010-92e3-69acabde2bd1@linux.intel.com> (raw)
In-Reply-To: <YyyGqDP8AgjsFAkM@nvidia.com>
On 2022/9/23 0:00, Jason Gunthorpe wrote:
> On Tue, Sep 06, 2022 at 08:44:54PM +0800, Lu Baolu wrote:
>
>> +/**
>> + * iommu_sva_bind_device() - Bind a process address space to a device
>> + * @dev: the device
>> + * @mm: the mm to bind, caller must hold a reference to mm_users
>> + *
>> + * Create a bond between device and address space, allowing the device to access
>> + * the mm using the returned PASID. If a bond already exists between @device and
>> + * @mm, it is returned and an additional reference is taken. Caller must call
>> + * iommu_sva_unbind_device() to release each reference.
>> + *
>> + * iommu_dev_enable_feature(dev, IOMMU_DEV_FEAT_SVA) must be called first, to
>> + * initialize the required SVA features.
> Thsi is something else that needs cleaning up. IOMMU_DEV_FEAT_SVA
> shouldn't exist.
>
> We need to figure out an appropriate way to allow PRI. IMHO the domain
> attach should do this, domains that require PRI should be distinct
> from domains that don't. When a PRI domain is attached the HW should
> be enabled to do PRI. The domain itself should carry the fault ops/etc
> that the caller supplies to respond to the PRI.
>
> That is something to address in the PRI series though..
From Intel IOMMU driver's point of view, with above done,
IOMMU_DEV_FEAT_SVA could be removed. However, it will take more time to
consider other needs.
>
> Reviewed-by: Jason Gunthorpe<jgg@nvidia.com>
Best regards,
baolu
next prev parent reply other threads:[~2022-09-23 2:31 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-06 12:44 [PATCH v13 00/13] iommu: SVA and IOPF refactoring Lu Baolu
2022-09-06 12:44 ` [PATCH v13 01/13] iommu: Add max_pasids field in struct iommu_device Lu Baolu
2022-09-06 12:44 ` [PATCH v13 02/13] iommu: Add max_pasids field in struct dev_iommu Lu Baolu
2022-09-06 12:44 ` [PATCH v13 03/13] iommu: Remove SVM_FLAG_SUPERVISOR_MODE support Lu Baolu
2022-09-06 12:44 ` [PATCH v13 04/13] PCI: Enable PASID only when ACS RR & UF enabled on upstream path Lu Baolu
2022-09-06 12:44 ` [PATCH v13 05/13] iommu: Add attach/detach_dev_pasid iommu interfaces Lu Baolu
2022-09-22 15:49 ` Jason Gunthorpe
2022-09-06 12:44 ` [PATCH v13 06/13] iommu: Add IOMMU SVA domain support Lu Baolu
2022-09-06 12:44 ` [PATCH v13 07/13] iommu/vt-d: Add " Lu Baolu
2022-09-22 15:49 ` Jason Gunthorpe
2022-09-23 2:21 ` Baolu Lu
2022-09-23 12:15 ` Jason Gunthorpe
2022-09-23 12:41 ` Baolu Lu
2022-09-23 13:07 ` Jason Gunthorpe
2022-09-23 13:12 ` Baolu Lu
2022-09-06 12:44 ` [PATCH v13 08/13] arm-smmu-v3/sva: " Lu Baolu
2022-09-22 15:53 ` Jason Gunthorpe
2022-09-06 12:44 ` [PATCH v13 09/13] iommu/sva: Refactoring iommu_sva_bind/unbind_device() Lu Baolu
2022-09-06 16:36 ` Jean-Philippe Brucker
2022-09-07 1:27 ` Baolu Lu
2022-09-07 9:54 ` Jean-Philippe Brucker
2022-09-07 17:33 ` Jason Gunthorpe
2022-09-08 16:25 ` Jean-Philippe Brucker
2022-09-08 16:41 ` Jason Gunthorpe
2022-09-09 1:54 ` Baolu Lu
2022-09-22 16:00 ` Jason Gunthorpe
2022-09-23 2:31 ` Baolu Lu [this message]
2022-09-06 12:44 ` [PATCH v13 10/13] iommu: Remove SVA related callbacks from iommu ops Lu Baolu
2022-09-06 12:44 ` [PATCH v13 11/13] iommu: Prepare IOMMU domain for IOPF Lu Baolu
2022-09-22 16:05 ` Jason Gunthorpe
2022-09-06 12:44 ` [PATCH v13 12/13] iommu: Per-domain I/O page fault handling Lu Baolu
2022-09-06 12:44 ` [PATCH v13 13/13] iommu: Rename iommu-sva-lib.{c,h} Lu Baolu
2022-09-12 3:05 ` [PATCH v13 00/13] iommu: SVA and IOPF refactoring Baolu Lu
2022-09-23 13:08 ` Baolu Lu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ca854564-f231-1010-92e3-69acabde2bd1@linux.intel.com \
--to=baolu.lu@linux.intel.com \
--cc=ashok.raj@intel.com \
--cc=bhelgaas@google.com \
--cc=dave.jiang@intel.com \
--cc=eric.auger@redhat.com \
--cc=fenghua.yu@intel.com \
--cc=hch@infradead.org \
--cc=iommu@lists.linux.dev \
--cc=jacob.jun.pan@intel.com \
--cc=jean-philippe@linaro.com \
--cc=jean-philippe@linaro.org \
--cc=jgg@nvidia.com \
--cc=joro@8bytes.org \
--cc=kevin.tian@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=robin.murphy@arm.com \
--cc=tony.zhu@intel.com \
--cc=vkoul@kernel.org \
--cc=will@kernel.org \
--cc=yi.l.liu@intel.com \
--cc=zhangfei.gao@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).