[PATCH v4 3/7] dt-bindings: iommu: Add spacemit/t100 features

Lv Zheng
2026-02-05T09:11:34Z

Adds device tree bindings for SpacemiT T100 specific features by
introducing spacemit,100 compatible. T100 contains distributed IOATCs,
each of which exposes pmiv interrupt.

Signed-off-by: Lv Zheng <lv.zheng@linux.spacemit.com>
Signed-off-by: Jingyu Li <joey.li@spacemit.com>
---
.../bindings/iommu/riscv,iommu.yaml | 53 ++++++++++++++++++-
1 file changed, 51 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
index d4838c3b3741..67d226a1a90d 100644
--- a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
@@ -32,6 +32,12 @@ properties:
# should be specified along with 'reg' property providing MMIO location.
compatible:
oneOf:
+ - description: SpacemiT distributed IOMMUs
+ items:
+ - enum:
+ - spacemit,t100
+ - const: spacemit,riscv-iommu
+ - const: riscv,iommu
- items:
- enum:
- qemu,riscv-iommu
@@ -57,11 +63,21 @@ properties:

interrupts:
minItems: 1
- maxItems: 4
+ maxItems: 68
description:
Wired interrupt vectors available for RISC-V IOMMU to notify the
RISC-V HARTS. The cause to interrupt vector is software defined
- using IVEC IOMMU register.
+ using ICVEC IOMMU register. For WSI only mode, the number of the
+ interrupt vectors should be 1 while for MSI possible mode, the
+ maximum of the interrupt vectors should be 4 with the cause indexed
+ as "CIV=0, FIV=1, PIV=2, PMIV=3".
+ SpacemiT distributed IOMMU includes additional interrupts for
+ IOATCs. Each IOATC exposes PMIV wired vector as standalone
+ interrupt and the maximum number of IOATCs can be up to 64. Thus for
+ WSI only mode, the maximum number of the interrupt vectors should be
+ 65 while for MSI possible mode, the maximum number of the interrupt
+ vectors should be 68 with the cause indexed as "IOATS CIV=0,
+ IOATS FIV=1, IOATS PIV=2, IOATS PMIV=3, IOATC0..n PMIV=4..4+n".

msi-parent: true

@@ -75,6 +91,18 @@ required:

additionalProperties: false

+allOf:
+ - if:
+ properties:
+ compatible:
+ not:
+ contains:
+ const: spacemit,riscv-iommu
+ then:
+ properties:
+ interrupts:
+ maxItems: 4
+
examples:
- |+
/* Example 1 (IOMMU device with wired interrupts) */
@@ -145,3 +173,24 @@ examples:
};
};
};
+
+ - |+
+ /* Example 5 (SpacemiT distributed IOMMU) */
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ iommu4: iommu@1bccd000 {
+ compatible = "spacemit,t100", "spacemit,riscv-iommu", "riscv,iommu";
+ reg = <0x1bccd000 0x1000>;
+ interrupts = <58 IRQ_TYPE_LEVEL_HIGH>,
+ <62 IRQ_TYPE_LEVEL_HIGH>, <63 IRQ_TYPE_LEVEL_HIGH>,
+ <62 IRQ_TYPE_LEVEL_HIGH>, <63 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&saplic>;
+ #iommu-cells = <0x01>;
+ };
+
+ /* Device with four IOMMU device IDs */
+ master2 {
+ #iommu-cells = <1>;
+ iommus = <&iommu4 0xc0010>, <&iommu4 0xc0011>,
+ <&iommu4 0xc0012>, <&iommu4 0xc0013>;
+ };
--
2.43.0