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From: Suravee Suthikulpanit via iommu <iommu@lists.linux-foundation.org>
To: Joerg Roedel <joro@8bytes.org>
Cc: iommu@lists.linux-foundation.org, jon.grimm@amd.com,
	linux-kernel@vger.kernel.org, vasant.hegde@amd.com
Subject: Re: [PATCH v2] iommu/amd: Set translation valid bit only when IO page tables are in used
Date: Thu, 26 May 2022 10:29:09 +0700	[thread overview]
Message-ID: <dac2c654-cb9c-6554-0afd-9e8db012374a@amd.com> (raw)
In-Reply-To: <YodMvV/8eii4KCLg@8bytes.org>

Joerg,

On 5/20/22 3:09 PM, Joerg Roedel wrote:
> Hi Suravee,
> 
> On Mon, May 16, 2022 at 07:27:51PM +0700, Suravee Suthikulpanit wrote:
> 
>> - Also, it seems that the current iommu v2 page table use case, where GVA->GPA=SPA
>> will no longer be supported on system w/ SNPSup=1. Any thoughts?
> 
> Support for that is not upstream yet, it should be easy to disallow this
> configuration and just use the v1 page-tables when SNP is active. This
> can be handled entirely inside the AMD IOMMU driver.
> 

Actually, I am referring to when user uses the IOMMU v2 table for shared virtual address
in current iommu_v2 driver (e.g. amd_iommu_init_device(), amd_iommu_bind_pasid).

Best Regards,
Suravee
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  parent reply	other threads:[~2022-05-26  3:29 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-09  7:48 [PATCH v2] iommu/amd: Set translation valid bit only when IO page tables are in used Suravee Suthikulpanit via iommu
2022-05-13 13:07 ` Joerg Roedel
2022-05-16 12:27   ` Suravee Suthikulpanit via iommu
2022-05-20  8:09     ` Joerg Roedel
2022-05-20  8:54       ` Robin Murphy
2022-05-20  8:58         ` Joerg Roedel
2022-05-20  9:18           ` Robin Murphy
2022-05-26  3:29       ` Suravee Suthikulpanit via iommu [this message]
2022-06-07  8:00         ` Joerg Roedel

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