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From: Baolu Lu <baolu.lu@linux.intel.com>
To: "Tian, Kevin" <kevin.tian@intel.com>,
	Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Jason Gunthorpe <jgg@nvidia.com>
Cc: Dmytro Maluka <dmaluka@chromium.org>,
	Samiullah Khawaja <skhawaja@google.com>,
	"iommu@lists.linux.dev" <iommu@lists.linux.dev>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/3] iommu/vt-d: Use 128-bit atomic updates for context entries
Date: Thu, 15 Jan 2026 11:26:50 +0800	[thread overview]
Message-ID: <db26b1e3-bd7a-44ee-b458-6cb0fedf6662@linux.intel.com> (raw)
In-Reply-To: <BN9PR11MB5276EFACF8AA21215568550F8C8FA@BN9PR11MB5276.namprd11.prod.outlook.com>

On 1/14/26 15:54, Tian, Kevin wrote:
>> From: Lu Baolu <baolu.lu@linux.intel.com>
>> Sent: Tuesday, January 13, 2026 11:01 AM
>>
>> On Intel IOMMU, device context entries are accessed by hardware in
>> 128-bit chunks. Currently, the driver updates these entries by
>> programming the 'lo' and 'hi' 64-bit fields individually.
>>
>> This creates a potential race condition where the IOMMU hardware may
>> fetch
>> a context entry while the CPU has only completed one of the two 64-bit
>> writes. This "torn" entry — consisting of half-old and half-new data —
>> could lead to unpredictable hardware behavior, especially when
>> transitioning the 'Present' bit or changing translation types.
> 
> this is not accurate. context entry is 128bits only. Scalable context
> entry is 256bits but only the lower 128bits are defined. so hardware always
> fetches the context entry atomically. Then if software ensures the right
> order of updates (clear present first then other bits), the hardware won't
> look at the partial entry after seeing present=0.
> 
> But now as Dmytro reported there is no barrier in place so two 64bits
> updates to the context entry might be reordered so hw could fetch
> an entry with old lower half (present=1) and new higher half.
> 
> then 128bit atomic operation avoids this ordering concern.

You're right. I will update the commit message to be more precise. Since
the hardware fetches the 128-bit context entry atomically, the issue is
essentially a software ordering problem.

We considered three approaches to solve this:

- Memory barriers (to enforce Present bit clearing order)
- WRITE_ONCE() (to prevent compiler reordering)
- 128-bit atomic updates

This patch uses the atomic update approach.

> 
>> @@ -1170,19 +1170,19 @@ static int domain_context_mapping_one(struct
>> dmar_domain *domain,
>>   		goto out_unlock;
>>
>>   	copied_context_tear_down(iommu, context, bus, devfn);
>> -	context_clear_entry(context);
>> -	context_set_domain_id(context, did);
>> +	context_set_domain_id(&new, did);
> 
> I wonder whether it's necessary to use atomic in the attach path, from
> fix p.o.v.
> 
> The assumption is that the context should have been cleared already
> before calling this function (and following ones). Does it make more
> sense to check the present bit, warning if set, then fail the operation?
> We could refactor them to do atomic update, but then it's for cleanup> instead of being part of a fix.

Yes. For the attach path, this is a cleanup rather than a fix.

> 
> Then this may be split into three patches:
> 
> - change context_clear_entry() to be atomic, to fix the teardown path
> - add present bit check in other functions in this patch, to scrutinize the
>    attach path
> - change those functions to be atomic, as a clean up

Perhaps this also paves the way for enabling hitless replace in the
attach_dev path?

> Does it make sense?

Yes, it is.

Thanks,
baolu

  reply	other threads:[~2026-01-15  3:26 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-13  3:00 [PATCH 0/3] iommu/vt-d: Ensure atomicity in context and PASID entry updates Lu Baolu
2026-01-13  3:00 ` [PATCH 1/3] iommu/vt-d: Use 128-bit atomic updates for context entries Lu Baolu
2026-01-13 19:27   ` Dmytro Maluka
2026-01-14  5:14     ` Baolu Lu
2026-01-14 10:55       ` Dmytro Maluka
2026-01-15  2:26         ` Baolu Lu
2026-01-15 13:12           ` Jason Gunthorpe
2026-01-14  7:54   ` Tian, Kevin
2026-01-15  3:26     ` Baolu Lu [this message]
2026-01-15  5:59       ` Tian, Kevin
2026-01-15 13:23         ` Jason Gunthorpe
2026-01-16  5:19           ` Tian, Kevin
2026-01-16 14:33             ` Jason Gunthorpe
2026-01-13  3:00 ` [PATCH 2/3] iommu/vt-d: Clear Present bit before tearing down PASID entry Lu Baolu
2026-01-13 19:34   ` Dmytro Maluka
2026-01-14  5:38     ` Baolu Lu
2026-01-14 11:12       ` Dmytro Maluka
2026-01-15  2:45         ` Baolu Lu
2026-01-15 21:35           ` Dmytro Maluka
2026-01-16  6:06             ` Baolu Lu
2026-01-20 13:49               ` Dmytro Maluka
2026-01-14  7:32   ` Tian, Kevin
2026-01-14  8:27     ` Baolu Lu
2026-01-15  5:49       ` Tian, Kevin
2026-01-13  3:00 ` [PATCH 3/3] iommu/vt-d: Rework hitless PASID entry replacement Lu Baolu
2026-01-13 15:05   ` Jason Gunthorpe
2026-01-14  6:03     ` Baolu Lu
2026-01-13 19:27   ` Samiullah Khawaja
2026-01-13 20:56     ` Jason Gunthorpe
2026-01-14  5:45     ` Baolu Lu
2026-01-14  7:26       ` Tian, Kevin
2026-01-14 13:17         ` Jason Gunthorpe
2026-01-14 18:51           ` Samiullah Khawaja
2026-01-14 19:07             ` Jason Gunthorpe
2026-01-15  5:44           ` Tian, Kevin
2026-01-15 13:28             ` Jason Gunthorpe
2026-01-16  6:16               ` Tian, Kevin
2026-01-13 19:39   ` Dmytro Maluka
2026-01-13 20:06     ` Dmytro Maluka

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