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[83.9.31.248]) by smtp.gmail.com with ESMTPSA id h7-20020a2e3a07000000b002a7aefa4bf7sm6633903lja.53.2023.05.04.10.41.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 May 2023 10:41:54 -0700 (PDT) Message-ID: Date: Thu, 4 May 2023 19:41:52 +0200 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.1 Subject: Re: [PATCH 1/2] iommu/arm-smmu-qcom: Fix missing adreno_smmu's Content-Language: en-US To: Rob Clark , dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov , Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , Sai Prakash Ranjan , Bjorn Andersson , Marijn Suijten , "moderated list:ARM SMMU DRIVERS" , "open list:IOMMU SUBSYSTEM" , open list References: <20230502160950.1758826-1-robdclark@gmail.com> From: Konrad Dybcio In-Reply-To: <20230502160950.1758826-1-robdclark@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 2.05.2023 18:09, Rob Clark wrote: > From: Rob Clark > > When the special handling of qcom,adreno-smmu was moved into > qcom_smmu_create(), it was overlooked that we didn't have all the > required entries in qcom_smmu_impl_of_match. So we stopped getting > adreno_smmu_priv on sc7180, breaking per-process pgtables. > > Fixes: 30b912a03d91 ("iommu/arm-smmu-qcom: Move the qcom,adreno-smmu check into qcom_smmu_create") > Signed-off-by: Rob Clark > --- I believe the issue here is the lack of qcom,sc7180-smmu-v2 instead. qcom,adreno-smmu does not have to imply the "qcom smmu v2" impl Konrad > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index d1b296b95c86..88c89424485b 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -512,20 +512,25 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { > { .compatible = "qcom,sm6115-smmu-500", .data = &qcom_smmu_500_impl0_data}, > { .compatible = "qcom,sm6125-smmu-500", .data = &qcom_smmu_500_impl0_data }, > { .compatible = "qcom,sm6350-smmu-v2", .data = &qcom_smmu_v2_data }, > { .compatible = "qcom,sm6350-smmu-500", .data = &qcom_smmu_500_impl0_data }, > { .compatible = "qcom,sm6375-smmu-500", .data = &qcom_smmu_500_impl0_data }, > { .compatible = "qcom,sm8150-smmu-500", .data = &qcom_smmu_500_impl0_data }, > { .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data }, > { .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data }, > { .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data }, > { .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data }, > + /* > + * Should come after the qcom,smmu-500 fallback so smmu-500 variants of > + * adreno-smmu get qcom_adreno_smmu_500_impl: > + */ > + { .compatible = "qcom,adreno-smmu", .data = &qcom_smmu_v2_data }, > { } > }; > > #ifdef CONFIG_ACPI > static struct acpi_platform_list qcom_acpi_platlist[] = { > { "LENOVO", "CB-01 ", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" }, > { "QCOM ", "QCOMEDK2", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU" }, > { } > }; > #endif