Re: [PATCH v6 0/9] iommu/amd: Use 128-bit cmpxchg operation to update DTE

["Suthikulpanit, Suravee" <suravee.suthikulpanit@amd.com>]

On 10/16/2024 9:22 PM, Jason Gunthorpe wrote:
>
> ....
>
> I wanted to see how far this was to being split up neatly like ARM is,
> I came up with this, which seems pretty good to me. This would
> probably be the next step to get to, then you'd lift the individual
> set functions higher up the call chain into their respective attach
> functions.

I like this idea and will look into adopting this code when I submit the 
nested translation stuff (right after this series) since it will affect 
the set_dte_entry().

> .....
> 
> static void set_dte_entry(struct amd_iommu *iommu,
> 			  struct iommu_dev_data *dev_data)
> {
> 	u32 old_domid;
> 	struct dev_table_entry new = {};
> 	struct protection_domain *domain = dev_data->domain;
> 	struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info;
> 	struct dev_table_entry *dte = &get_dev_table(iommu)[dev_data->devid];
> 
> 	make_clear_dte(dev_data, dte, &new);
> 	if (gcr3_info && gcr3_info->gcr3_tbl)
> 		set_dte_gcr3_table(iommu, dev_data, &new);
> 	else if (domain->iop.mode == PAGE_MODE_NONE)
> 		set_dte_identity(iommu, dev_data, &new);
> 	else
> 		set_dte_paging(iommu, dev_data, &new);

This will need to be change once we add nested translation support 
because we need to call both set_dte_paging() and set_dte_gcr3().

Thanks,
Suravee