From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 059143214 for ; Sun, 28 Aug 2022 13:57:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661695048; x=1693231048; h=message-id:date:mime-version:cc:subject:to:references: from:in-reply-to:content-transfer-encoding; bh=y4cNfjDDXR16p7aBOCe2GLlX4JBhY0BsBXSjUlii/Og=; b=RlBichpN+zQhXtoA6F2lMHFyog/ULZw5Lul/UXMaNEkFclETsPS3jRCx 3F4Fc6/ZLedbQl83gPOBDjyW8k0B/EVB/TM1Ipq7H2taKC9mmn8dNqReL aatRPLUcaqnSjk67s5ySd2mF9amEyFfO02zwPVUQB5OrxkEraJl3O4i0H ebbu4/n0VnYNf0E04je6v3TJc903FgkLS8lrJzMjNWj18tEAZtjpxjVPI zHcesrMfze3G4+KT7lAjI6hdpSRN471YlhOhPDAxHBPceGemLSRRDG34o qEB6/jrRaLyGcxD99xMWE+sIzSFe1RMGxVUwsyKkvbs677I9W9Scpn40/ w==; X-IronPort-AV: E=McAfee;i="6500,9779,10453"; a="381045872" X-IronPort-AV: E=Sophos;i="5.93,270,1654585200"; d="scan'208";a="381045872" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Aug 2022 06:57:27 -0700 X-IronPort-AV: E=Sophos;i="5.93,270,1654585200"; d="scan'208";a="672065818" Received: from cyue-mobl1.ccr.corp.intel.com (HELO [10.254.209.98]) ([10.254.209.98]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Aug 2022 06:57:23 -0700 Message-ID: Date: Sun, 28 Aug 2022 21:57:21 +0800 Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Cc: baolu.lu@linux.intel.com, Joerg Roedel , Christoph Hellwig , Bjorn Helgaas , Kevin Tian , Ashok Raj , Will Deacon , Robin Murphy , Jean-Philippe Brucker , Dave Jiang , Fenghua Yu , Vinod Koul , Eric Auger , Liu Yi L , Jacob jun Pan , Zhangfei Gao , Zhu Tony , iommu@lists.linux.dev, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Jean-Philippe Brucker Subject: Re: [PATCH v12 12/17] arm-smmu-v3/sva: Add SVA domain support Content-Language: en-US To: Jason Gunthorpe References: <20220826121141.50743-1-baolu.lu@linux.intel.com> <20220826121141.50743-13-baolu.lu@linux.intel.com> From: Baolu Lu In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 2022/8/26 22:56, Jason Gunthorpe wrote: > On Fri, Aug 26, 2022 at 08:11:36PM +0800, Lu Baolu wrote: > >> +static const struct iommu_domain_ops arm_smmu_sva_domain_ops = { >> + .set_dev_pasid = arm_smmu_sva_set_dev_pasid, > Do we want to permit drivers to not allow a SVA domain to be set on a > RID? > > It seems like a weird restriction to me Conceptually as long as the page table is compatible and user pages are pinned (or I/O page fault is supported), the device drivers are valid to set SVA domain to a RID. But I don't see a real use case as far as I can see. A reasonable use case is sharing EPT between KVM and IOMMU. That demands a new type of domain and implements its own .set_dev for page table attachment. Best regards, baolu