Re: [PATCH v9 5/5] iommu/arm-smmu: Add support for qcom,smmu-v2 variant

[Vivek Gautam <vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>]

Hi Yisheng,


On 4/11/2018 6:52 AM, Yisheng Xie wrote:
> Hi Tomasz,
>
> On 2018/4/10 21:14, Tomasz Figa wrote:
>> Hi Yisheng,
>>
>> Sorry, I think we missed your question here.
>>
>> On Wed, Mar 28, 2018 at 3:12 PM Yisheng Xie <xieyisheng1-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> wrote:
>>
>>> Hi Vivek,
>>> On 2018/3/28 12:37, Vivek Gautam wrote:
>>>> Hi Yisheng
>>>>
>>>>
>>>> On 3/28/2018 6:54 AM, Yisheng Xie wrote:
>>>>> Hi Vivek,
>>>>>
>>>>> On 2018/3/13 16:55, Vivek Gautam wrote:
>>>>>> +- power-domains:  Specifiers for power domains required to be
>> powered on for
>>>>>> +                  the SMMU to operate, as per generic power domain
>> bindings.
>>>>>> +
>>>>> In this patchset, power-domains is not used right? And you just do the
>> clock gating,
>>>>> but not power gating, right?
>>>> We are handling the power-domains too. Please see the example in this
>> binding doc.
>>
>>> I see, but I do not find the point in code of these patchset, do you mean
>> PMIC(e.g mmcc)
>>> will gate the power domain of SMMU(e.g. MDSS_GDSC of mmcc) when PMIC
>> suspend?
>>
>>
>> If respective SoC power domains is registered as a standard genpd PM
>> domain, then the runtime PM subsystem will take care of power domain
>> control at runtime suspend and resume.
>>
> Get it, thanks for your explain, I should have learned about this.

Sorry, i missed your subsequent question, and Tomasz has explained it now.
Let me know if you have further questions.

regards
Vivek
>
> Thanks
> Yisheng
>
>> Best regards,
>> Tomasz
>>
>> .
>>
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