From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vivek Gautam Subject: Re: [PATCH v9 5/5] iommu/arm-smmu: Add support for qcom,smmu-v2 variant Date: Wed, 11 Apr 2018 10:45:24 +0530 Message-ID: References: <20180313085534.11650-1-vivek.gautam@codeaurora.org> <20180313085534.11650-6-vivek.gautam@codeaurora.org> <61d30fff-1bf8-d2c1-bbe9-f93de836ae77@huawei.com> <7d5af071-ef98-8461-3ce9-e84fc0b3956a@codeaurora.org> <65a57964-805b-3a38-71a2-0c383af30539@huawei.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <65a57964-805b-3a38-71a2-0c383af30539-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Yisheng Xie , Tomasz Figa Cc: Mark Rutland , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-msm , Will Deacon , Linux Kernel Mailing List , "list-Y9sIeH5OGRo@public.gmane.org:IOMMU DRIVERS" , gaojianbo-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org List-Id: iommu@lists.linux-foundation.org Hi Yisheng, On 4/11/2018 6:52 AM, Yisheng Xie wrote: > Hi Tomasz, > > On 2018/4/10 21:14, Tomasz Figa wrote: >> Hi Yisheng, >> >> Sorry, I think we missed your question here. >> >> On Wed, Mar 28, 2018 at 3:12 PM Yisheng Xie wrote: >> >>> Hi Vivek, >>> On 2018/3/28 12:37, Vivek Gautam wrote: >>>> Hi Yisheng >>>> >>>> >>>> On 3/28/2018 6:54 AM, Yisheng Xie wrote: >>>>> Hi Vivek, >>>>> >>>>> On 2018/3/13 16:55, Vivek Gautam wrote: >>>>>> +- power-domains: Specifiers for power domains required to be >> powered on for >>>>>> + the SMMU to operate, as per generic power domain >> bindings. >>>>>> + >>>>> In this patchset, power-domains is not used right? And you just do the >> clock gating, >>>>> but not power gating, right? >>>> We are handling the power-domains too. Please see the example in this >> binding doc. >> >>> I see, but I do not find the point in code of these patchset, do you mean >> PMIC(e.g mmcc) >>> will gate the power domain of SMMU(e.g. MDSS_GDSC of mmcc) when PMIC >> suspend? >> >> >> If respective SoC power domains is registered as a standard genpd PM >> domain, then the runtime PM subsystem will take care of power domain >> control at runtime suspend and resume. >> > Get it, thanks for your explain, I should have learned about this. Sorry, i missed your subsequent question, and Tomasz has explained it now. Let me know if you have further questions. regards Vivek > > Thanks > Yisheng > >> Best regards, >> Tomasz >> >> . >> > -- > To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in > the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org > More majordomo info at http://vger.kernel.org/majordomo-info.html