From: Thomas Gleixner <tglx@linutronix.de>
To: Palmer Dabbelt <palmer@dabbelt.com>
Cc: peterz@infradead.org, jason@lakedaemon.net, marc.zyngier@arm.com,
Arnd Bergmann <arnd@arndb.de>,
yamada.masahiro@socionext.com, mmarek@suse.com,
albert@sifive.com, will.deacon@arm.com, boqun.feng@gmail.com,
oleg@redhat.com, mingo@redhat.com, daniel.lezcano@linaro.org,
gregkh@linuxfoundation.org, jslaby@suse.com, davem@davemloft.net,
mchehab@kernel.org, hverkuil@xs4all.nl, rdunlap@infradead.org,
viro@zeniv.linux.org.uk, mhiramat@kernel.org, fweisbec@gmail.com,
mcgrof@kernel.org, dledford@redhat.com,
bart.vanassche@sandisk.com, sstabellini@kernel.org,
mpe@ellerman.id.au, rmk+kernel@armlinux.org.uk,
paul.gortmaker@windriver.com, nicolas.dichtel@6wind.com,
linux@roeck-us.net, heiko.carstens@de.ibm.com,
schwidefsky@de.ibm.com, geert@linux-m68k.org,
akpm@linux-foundation.org, andriy.shevchenko@linux.intel.com,
jiri@mellanox.com, vgupta@synopsys.com, airlied@redhat.com,
jk@ozlabs.org, chris@chris-wilson.co.uk, Jason@zx2c4.com,
paulmck@linux.vnet.ibm.com, ncardwell@google.com,
linux-kernel@vger.kernel.org, linux-kbuild@vger.kernel.org,
patches@groups.riscv.org
Subject: Re: [PATCH v7 04/15] irqchip: RISC-V Local Interrupt Controller Driver
Date: Wed, 16 Aug 2017 17:12:18 +0200 (CEST) [thread overview]
Message-ID: <alpine.DEB.2.20.1708161702350.1987@nanos> (raw)
In-Reply-To: <20170801010009.3302-5-palmer@dabbelt.com>
On Mon, 31 Jul 2017, Palmer Dabbelt wrote:
> +static void riscv_software_interrupt(void)
> +{
> +#ifdef CONFIG_SMP
> + irqreturn_t ret;
> +
> + ret = handle_ipi();
> +
> + WARN_ON(ret == IRQ_NONE);
WARN_ON(handle_ipi() == IRQ_NONE);
perhaps?
> +#else
> + /*
> + * We currently only use software interrupts to pass inter-processor
> + * interrupts, so if a non-SMP system gets a software interrupt then we
> + * don't know what to do.
> + */
> + pr_warning("Software Interrupt without CONFIG_SMP\n");
> +#endif
> +}
> +static void riscv_irq_enable(struct irq_data *d)
> +{
> + struct riscv_irq_data *data = irq_data_get_irq_chip_data(d);
> +
> + /*
> + * It's only possible to write SIE on the current hart. This jumps
> + * over to the target hart if it's not the current one. It's invalid
> + * to write SIE on a hart that's not currently running.
> + */
> + if (data->hart == smp_processor_id())
> + riscv_irq_unmask(d);
> + else if (cpu_online(data->hart))
> + smp_call_function_single(data->hart,
> + riscv_irq_enable_helper,
> + d,
> + true);
> + else
> + WARN_ON_ONCE(1);
If you write a small helper:
static void riscv_remote_ctrl(unsigned int cpu, void (*fn)(void *d),
struct irq_data *data)
{
smp_call_function_single(cpu, cb, data, true);
}
Then both riscv_irq_enable() and riscv_irq_disable() become readable
functions.
if (data->hart == smp_processor_id())
riscv_irq_unmask(d);
else if (cpu_online(data->hart))
riscv_remote_ctrl(data->hart, riscv_irq_enable_helper, d);
else
WARN_ON_ONCE(1);
Hmm?
> +static int riscv_intc_init(struct device_node *node, struct device_node *parent)
> +{
> + int hart;
> + struct riscv_irq_data *data;
> +
> + if (parent)
> + return 0;
> +
> + hart = riscv_of_processor_hart(node->parent);
> + if (hart < 0)
> + return -EIO;
> +
> + data = &per_cpu(riscv_irq_data, hart);
> + snprintf(data->name, sizeof(data->name), "riscv,cpu_intc,%d", hart);
> + data->hart = hart;
> + data->chip.name = data->name;
> + data->chip.irq_mask = riscv_irq_mask;
> + data->chip.irq_unmask = riscv_irq_unmask;
> + data->chip.irq_enable = riscv_irq_enable;
> + data->chip.irq_disable = riscv_irq_disable;
> + data->domain = irq_domain_add_linear(
> + node,
> + 8*sizeof(uintptr_t),
> + &riscv_irqdomain_ops,
> + data);
This is really horrible to read. What's wrong with using the full 80 chars?
data->domain = irq_domain_add_linear(node, 8 * sizeof(uintptr_t),
&riscv_irqdomain_ops, data);
> + if (!data->domain)
> + goto error_add_linear;
> + pr_info("%s: %d local interrupts mapped\n",
> + data->name, 8*(int)sizeof(uintptr_t));
Can we please make that '8 * sizeof()' a constant and use it in both
places? Which makes the pr_info also fit into a single line.
> + return 0;
> +
> +error_add_linear:
> + pr_warning("%s: unable to add IRQ domain\n",
> + data->name);
Single line please. Enough room.
> + return -(ENXIO);
No braces.
Thanks,
tglx
next prev parent reply other threads:[~2017-08-16 15:14 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-01 0:59 RISC-V Linux Port v7 Palmer Dabbelt
2017-08-01 0:59 ` [PATCH v7 01/15] MAINTAINERS: Add RISC-V Palmer Dabbelt
2017-08-01 13:03 ` Andy Shevchenko
2017-08-03 13:07 ` [patches] " Jonathan Neuschäfer
2017-08-01 0:59 ` [PATCH v7 02/15] lib: Add shared copies of some GCC library routines Palmer Dabbelt
2017-08-01 13:06 ` Andy Shevchenko
2017-08-20 19:54 ` Palmer Dabbelt
2017-08-01 0:59 ` [PATCH v7 03/15] clocksource: New RISC-V SBI timer driver Palmer Dabbelt
2017-08-16 15:23 ` Thomas Gleixner
2017-08-01 0:59 ` [PATCH v7 04/15] irqchip: RISC-V Local Interrupt Controller Driver Palmer Dabbelt
2017-08-01 15:35 ` Randy Dunlap
2017-08-16 15:12 ` Thomas Gleixner [this message]
2017-08-01 0:59 ` [PATCH v7 05/15] irqchip: New RISC-V PLIC Driver Palmer Dabbelt
2017-08-01 13:29 ` Andy Shevchenko
2017-08-01 15:20 ` Randy Dunlap
2017-08-03 22:22 ` [patches] " Jonathan Neuschäfer
2017-08-01 1:00 ` [PATCH v7 06/15] tty: New RISC-V SBI console driver Palmer Dabbelt
2017-08-01 13:33 ` Andy Shevchenko
2017-08-01 1:00 ` [PATCH v7 07/15] RISC-V: Init and Halt Code Palmer Dabbelt
2017-08-01 1:00 ` [PATCH v7 08/15] RISC-V: Atomic and Locking Code Palmer Dabbelt
2017-08-01 5:31 ` Boqun Feng
2017-08-01 1:00 ` [PATCH v7 09/15] RISC-V: Generic library routines and assembly Palmer Dabbelt
2017-08-01 1:00 ` [PATCH v7 10/15] RISC-V: ELF and module implementation Palmer Dabbelt
2017-08-01 1:00 ` [PATCH v7 11/15] RISC-V: Task implementation Palmer Dabbelt
2017-08-01 1:00 ` [PATCH v7 12/15] RISC-V: Device, timer, IRQs, and the SBI Palmer Dabbelt
2017-08-01 1:00 ` [PATCH v7 13/15] RISC-V: Paging and MMU Palmer Dabbelt
2017-08-01 1:00 ` [PATCH v7 14/15] RISC-V: User-facing API Palmer Dabbelt
2017-08-01 1:00 ` [PATCH v7 15/15] RISC-V: Build Infastructure Palmer Dabbelt
2017-08-01 15:27 ` Randy Dunlap
2017-08-01 23:03 ` Masahiro Yamada
-- strict thread matches above, loose matches on Subject: below --
2017-08-01 17:08 [PATCH v7 04/15] irqchip: RISC-V Local Interrupt Controller Driver Rob Herring
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