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([2804:14d:887:95a9:e1a5:e9d5:ba9a:df82]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7347a839dffsm2271324b3a.172.2025.02.25.17.09.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Feb 2025 17:10:02 -0800 (PST) From: Leonardo Felipe Takao Hirata To: tglx@linutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vz@mleia.com Cc: Leonardo Felipe Takao Hirata , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, skhan@linuxfoundation.org, linux-kernel-mentees@lists.linuxfoundation.org Subject: [PATCH v2] dt-bindings: interrupt-controller: Convert nxp,lpc3220-mic.txt to yaml format Date: Tue, 25 Feb 2025 22:09:40 -0300 Message-ID: <20250226010956.50566-1-leo.fthirata@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel-mentees@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Convert NXP LPC3220-MIC to DT schema. Signed-off-by: Leonardo Felipe Takao Hirata --- Changes in v2: - Fix SoB - Remove reg description - List #interrupt-cell items - Add interrupt restriction per variant - Remove extra examples --- .../interrupt-controller/nxp,lpc3220-mic.txt | 58 -------------- .../interrupt-controller/nxp,lpc3220-mic.yaml | 80 +++++++++++++++++++ 2 files changed, 80 insertions(+), 58 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt deleted file mode 100644 index 0bfb3ba55f4c..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt +++ /dev/null @@ -1,58 +0,0 @@ -* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers - -Required properties: -- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic". -- reg: should contain IC registers location and length. -- interrupt-controller: identifies the node as an interrupt controller. -- #interrupt-cells: the number of cells to define an interrupt, should be 2. - The first cell is the IRQ number, the second cell is used to specify - one of the supported IRQ types: - IRQ_TYPE_EDGE_RISING = low-to-high edge triggered, - IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered, - IRQ_TYPE_LEVEL_HIGH = active high level-sensitive, - IRQ_TYPE_LEVEL_LOW = active low level-sensitive. - Reset value is IRQ_TYPE_LEVEL_LOW. - -Optional properties: -- interrupts: empty for MIC interrupt controller, cascaded MIC - hardware interrupts for SIC1 and SIC2 - -Examples: - - /* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */ - mic: interrupt-controller@40008000 { - compatible = "nxp,lpc3220-mic"; - reg = <0x40008000 0x4000>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - sic1: interrupt-controller@4000c000 { - compatible = "nxp,lpc3220-sic"; - reg = <0x4000c000 0x4000>; - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&mic>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>, - <30 IRQ_TYPE_LEVEL_LOW>; - }; - - sic2: interrupt-controller@40010000 { - compatible = "nxp,lpc3220-sic"; - reg = <0x40010000 0x4000>; - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&mic>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>, - <31 IRQ_TYPE_LEVEL_LOW>; - }; - - /* ADC */ - adc@40048000 { - compatible = "nxp,lpc3220-adc"; - reg = <0x40048000 0x1000>; - interrupt-parent = <&sic1>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.yaml b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.yaml new file mode 100644 index 000000000000..489bd329bc4e --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/nxp,lpc3220-mic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers + +maintainers: + - Vladimir Zapolskiy + +properties: + compatible: + enum: + - nxp,lpc3220-mic + - nxp,lpc3220-sic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + items: + - description: + IRQ number. + - description: | + IRQ type. Can be one of: + + IRQ_TYPE_EDGE_RISING = Low-to-high edge triggered, + IRQ_TYPE_EDGE_FALLING = High-to-low edge triggered, + IRQ_TYPE_LEVEL_HIGH = Active high level-sensitive, + IRQ_TYPE_LEVEL_LOW = Active low level-sensitive. + + Reset value is IRQ_TYPE_LEVEL_LOW. + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +allOf: + - if: + properties: + compatible: + contains: + const: nxp,lpc3220-sic + then: + required: + - interrupts + else: + properties: + interrupts: false + +additionalProperties: false + +examples: + - | + #include + + mic: interrupt-controller@40008000 { + compatible = "nxp,lpc3220-mic"; + reg = <0x40008000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sic1: interrupt-controller@4000c000 { + compatible = "nxp,lpc3220-sic"; + reg = <0x4000c000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&mic>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>, + <30 IRQ_TYPE_LEVEL_LOW>; + }; -- 2.43.0