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Fri, 15 Aug 2025 11:28:01 -0700 (PDT) Received: from archlinux ([2401:4900:93f2:6a91:9b6f:8f9d:11b:d64a]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-32343994891sm1791582a91.8.2025.08.15.11.27.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Aug 2025 11:28:01 -0700 (PDT) From: Suchit Karunakaran To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, guoren@kernel.org, linux-perf-users@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-csky@vger.kernel.org, skhan@linuxfoundation.org, linux-kernel-mentees@lists.linux.dev, Suchit Karunakaran Subject: [PATCH RESEND] perf/util: make TYPE_STATE_MAX_REGS architecture-dependent Date: Fri, 15 Aug 2025 23:57:42 +0530 Message-ID: <20250815182742.45541-1-suchitkarunakaran@gmail.com> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: linux-kernel-mentees@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Replace the fixed definition of TYPE_STATE_MAX_REGS with architecture- specific values for better accuracy across multiple CPU architectures including PowerPC, ARM, x86, RISC-V, MIPS, and others. This change ensures the type state registers array size matches the actual register count of the target platform. Signed-off-by: Suchit Karunakaran --- tools/perf/util/annotate-data.h | 45 ++++++++++++++++++++++++++++++--- 1 file changed, 41 insertions(+), 4 deletions(-) diff --git a/tools/perf/util/annotate-data.h b/tools/perf/util/annotate-data.h index 541fee1a5f0a..0dfb12a8f1cc 100644 --- a/tools/perf/util/annotate-data.h +++ b/tools/perf/util/annotate-data.h @@ -189,11 +189,48 @@ struct type_state_stack { u8 kind; }; -/* FIXME: This should be arch-dependent */ -#ifdef __powerpc__ -#define TYPE_STATE_MAX_REGS 32 +#if defined(__powerpc__) || defined(__powerpc64__) +#define TYPE_STATE_MAX_REGS 32 +#elif defined(__aarch64__) +#define TYPE_STATE_MAX_REGS 31 +#elif defined(__arm__) +#define TYPE_STATE_MAX_REGS 16 +#elif defined(__x86_64__) +#define TYPE_STATE_MAX_REGS 16 +#elif defined(__i386__) +#define TYPE_STATE_MAX_REGS 8 +#elif defined(__riscv) +#define TYPE_STATE_MAX_REGS 32 +#elif defined(__mips__) +#define TYPE_STATE_MAX_REGS 32 +#elif defined(__sparc__) || defined(__sparc64__) +#define TYPE_STATE_MAX_REGS 32 +#elif defined(__alpha__) +#define TYPE_STATE_MAX_REGS 32 +#elif defined(__s390__) || defined(__s390x__) +#define TYPE_STATE_MAX_REGS 16 +#elif defined(__sh__) +#define TYPE_STATE_MAX_REGS 16 +#elif defined(__nios2__) +#define TYPE_STATE_MAX_REGS 32 +#elif defined(__hexagon__) +#define TYPE_STATE_MAX_REGS 32 +#elif defined(__openrisc__) +#define TYPE_STATE_MAX_REGS 32 +#elif defined(__csky__) +#define TYPE_STATE_MAX_REGS 32 +#elif defined(__loongarch__) +#define TYPE_STATE_MAX_REGS 32 +#elif defined(__arc__) +#define TYPE_STATE_MAX_REGS 32 +#elif defined(__microblaze__) +#define TYPE_STATE_MAX_REGS 32 +#elif defined(__xtensa__) +#define TYPE_STATE_MAX_REGS 16 +#elif defined(__m68k__) +#define TYPE_STATE_MAX_REGS 16 #else -#define TYPE_STATE_MAX_REGS 16 +#define TYPE_STATE_MAX_REGS 16 #endif /* -- 2.50.1