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Sat, 30 May 2026 04:40:18 -0700 (PDT) From: SeungJu Cheon To: jic23@kernel.org, linux-iio@vger.kernel.org Cc: dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, apokusinski01@gmail.com, me@brighamcampbell.com, skhan@linuxfoundation.org, linux-kernel-mentees@lists.linux.dev, SeungJu Cheon Subject: [PATCH 3/4] iio: pressure: mpl3115: generalize interrupt pin routing Date: Sat, 30 May 2026 20:39:37 +0900 Message-ID: <20260530113938.171540-4-suunj1331@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260530113938.171540-1-suunj1331@gmail.com> References: <20260530113938.171540-1-suunj1331@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel-mentees@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Write CTRL_REG5 explicitly for both INT1 and INT2 rather than relying on power-on defaults when INT2 is selected. This avoids incorrect interrupt routing after a suspend/resume cycle where the register may not return to its default state. Route both DRDY and FIFO interrupts to the selected pin. The FIFO routing is not yet used but is required by the hardware FIFO support added in the following patch. Consolidate polarity configuration into a single code path that handles both interrupt pins uniformly. No functional change intended. Signed-off-by: SeungJu Cheon --- drivers/iio/pressure/mpl3115.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/iio/pressure/mpl3115.c b/drivers/iio/pressure/mpl3115.c index 52a3d0d59769..90e83e34ec43 100644 --- a/drivers/iio/pressure/mpl3115.c +++ b/drivers/iio/pressure/mpl3115.c @@ -67,6 +67,7 @@ #define MPL3115_CTRL4_INT_EN_TTH BIT(2) #define MPL3115_CTRL5_INT_CFG_DRDY BIT(7) +#define MPL3115_CTRL5_INT_CFG_FIFO BIT(6) static const unsigned int mpl3115_samp_freq_table[][2] = { { 1, 0 }, @@ -624,6 +625,7 @@ static int mpl3115_trigger_probe(struct mpl3115_data *data, { struct fwnode_handle *fwnode = dev_fwnode(&data->client->dev); int ret, irq, irq_type, irq_pin = MPL3115_IRQ_INT1; + u8 ctrl_reg5; irq = fwnode_irq_get_byname(fwnode, "INT1"); if (irq < 0) { @@ -634,6 +636,9 @@ static int mpl3115_trigger_probe(struct mpl3115_data *data, irq_pin = MPL3115_IRQ_INT2; } + ctrl_reg5 = irq_pin == MPL3115_IRQ_INT1 ? + MPL3115_CTRL5_INT_CFG_DRDY | MPL3115_CTRL5_INT_CFG_FIFO : 0; + irq_type = irq_get_trigger_type(irq); if (irq_type != IRQF_TRIGGER_RISING && irq_type != IRQF_TRIGGER_FALLING) return -EINVAL; @@ -643,23 +648,19 @@ static int mpl3115_trigger_probe(struct mpl3115_data *data, if (ret < 0) return ret; - if (irq_pin == MPL3115_IRQ_INT1) { - ret = i2c_smbus_write_byte_data(data->client, - MPL3115_CTRL_REG5, - MPL3115_CTRL5_INT_CFG_DRDY); - if (ret) - return ret; + ret = i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG5, + ctrl_reg5); + if (ret) + return ret; - if (irq_type == IRQF_TRIGGER_RISING) { - ret = i2c_smbus_write_byte_data(data->client, - MPL3115_CTRL_REG3, - MPL3115_CTRL3_IPOL1); - if (ret) - return ret; - } - } else if (irq_type == IRQF_TRIGGER_RISING) { - ret = i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG3, - MPL3115_CTRL3_IPOL2); + if (irq_type == IRQF_TRIGGER_RISING) { + u8 ipol = irq_pin == MPL3115_IRQ_INT1 ? + MPL3115_CTRL3_IPOL1 : + MPL3115_CTRL3_IPOL2; + + ret = i2c_smbus_write_byte_data(data->client, + MPL3115_CTRL_REG3, + ipol); if (ret) return ret; } -- 2.52.0