Linux Kernel Mentees list
 help / color / mirror / Atom feed
From: Jonathan Cameron <jic23@kernel.org>
To: SeungJu Cheon <suunj1331@gmail.com>
Cc: linux-iio@vger.kernel.org, dlechner@baylibre.com,
	nuno.sa@analog.com, andy@kernel.org, apokusinski01@gmail.com,
	me@brighamcampbell.com, skhan@linuxfoundation.org,
	linux-kernel-mentees@lists.linux.dev
Subject: Re: [PATCH 3/4] iio: pressure: mpl3115: generalize interrupt pin routing
Date: Sat, 30 May 2026 16:32:08 +0100	[thread overview]
Message-ID: <20260530163208.698e9b31@jic23-huawei> (raw)
In-Reply-To: <20260530113938.171540-4-suunj1331@gmail.com>

On Sat, 30 May 2026 20:39:37 +0900
SeungJu Cheon <suunj1331@gmail.com> wrote:

> Write CTRL_REG5 explicitly for both INT1 and INT2 rather than
> relying on power-on defaults when INT2 is selected.
> 
> This avoids incorrect interrupt routing after a suspend/resume
> cycle where the register may not return to its default state.

Need more information on this.  What do you actually mean by not return
to it's default state?  There are a lot of registers in this device
that affect config - are all the others restored after resume?

I suspect you are actually talking about a soft reboot where the
driver is reloading. Given there is a reset call just above this
that should never be an issue.

> 
> Route both DRDY and FIFO interrupts to the selected pin. The
> FIFO routing is not yet used but is required by the hardware
> FIFO support added in the following patch.
Do it in that patch then, not now.  By all means introduce a
local variable that you change in that patch, but don't set
the fifo bit.
> 
> Consolidate polarity configuration into a single code path
> that handles both interrupt pins uniformly.
> 
> No functional change intended.
> 
> Signed-off-by: SeungJu Cheon <suunj1331@gmail.com>
> ---
>  drivers/iio/pressure/mpl3115.c | 33 +++++++++++++++++----------------
>  1 file changed, 17 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/iio/pressure/mpl3115.c b/drivers/iio/pressure/mpl3115.c
> index 52a3d0d59769..90e83e34ec43 100644
> --- a/drivers/iio/pressure/mpl3115.c
> +++ b/drivers/iio/pressure/mpl3115.c
> @@ -67,6 +67,7 @@
>  #define MPL3115_CTRL4_INT_EN_TTH BIT(2)
>  
>  #define MPL3115_CTRL5_INT_CFG_DRDY BIT(7)
> +#define MPL3115_CTRL5_INT_CFG_FIFO BIT(6)

Not in this patch.  

>  
>  static const unsigned int mpl3115_samp_freq_table[][2] = {
>  	{ 1,      0 },
> @@ -624,6 +625,7 @@ static int mpl3115_trigger_probe(struct mpl3115_data *data,
>  {
>  	struct fwnode_handle *fwnode = dev_fwnode(&data->client->dev);
>  	int ret, irq, irq_type, irq_pin = MPL3115_IRQ_INT1;
> +	u8 ctrl_reg5;
>  
>  	irq = fwnode_irq_get_byname(fwnode, "INT1");
>  	if (irq < 0) {
> @@ -634,6 +636,9 @@ static int mpl3115_trigger_probe(struct mpl3115_data *data,
>  		irq_pin = MPL3115_IRQ_INT2;
>  	}
>  
> +	ctrl_reg5 = irq_pin == MPL3115_IRQ_INT1 ?
> +	    MPL3115_CTRL5_INT_CFG_DRDY | MPL3115_CTRL5_INT_CFG_FIFO : 0;

That's complex enough that I'd prefer it as a simple if / else
as will be easier to read.  Also you are enabling the fifo interrupt.
That should be in the next patch, not here.

> +
>  	irq_type = irq_get_trigger_type(irq);
>  	if (irq_type != IRQF_TRIGGER_RISING && irq_type != IRQF_TRIGGER_FALLING)
>  		return -EINVAL;
> @@ -643,23 +648,19 @@ static int mpl3115_trigger_probe(struct mpl3115_data *data,
>  	if (ret < 0)
>  		return ret;
>  
> -	if (irq_pin == MPL3115_IRQ_INT1) {
> -		ret = i2c_smbus_write_byte_data(data->client,
> -						MPL3115_CTRL_REG5,
> -						MPL3115_CTRL5_INT_CFG_DRDY);
> -		if (ret)
> -			return ret;
> +	ret = i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG5,
> +					ctrl_reg5);
> +	if (ret)
> +		return ret;
>  
> -		if (irq_type == IRQF_TRIGGER_RISING) {
> -			ret = i2c_smbus_write_byte_data(data->client,
> -							MPL3115_CTRL_REG3,
> -							MPL3115_CTRL3_IPOL1);
> -			if (ret)
> -				return ret;
> -		}
> -	} else if (irq_type == IRQF_TRIGGER_RISING) {
> -		ret = i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG3,
> -						MPL3115_CTRL3_IPOL2);
> +	if (irq_type == IRQF_TRIGGER_RISING) {
> +		u8 ipol = irq_pin == MPL3115_IRQ_INT1 ?
> +			  MPL3115_CTRL3_IPOL1 :
> +			  MPL3115_CTRL3_IPOL2;

Oh that's fun. The data sheet has bit 1 as IPOL2 in the compact
table 49, but PP_OD2 as bits 0 and bit 1 in table 50.  If you are bored,
might be wroth pointing that typo out to them!

> +
> +		ret = i2c_smbus_write_byte_data(data->client,
> +						MPL3115_CTRL_REG3,
> +						ipol);
		ret = i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG3, ipol);

Fine to go a bit long where it helps readability (stay under 100 chars though!)



>  		if (ret)
>  			return ret;
>  	}


  parent reply	other threads:[~2026-05-30 15:32 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-30 11:39 [PATCH 0/4] iio: pressure: mpl3115: add hardware FIFO support SeungJu Cheon
2026-05-30 11:39 ` [PATCH 1/4] iio: pressure: mpl3115: convert probe to fully devm managed SeungJu Cheon
2026-05-30 12:12   ` Andy Shevchenko
2026-05-31 10:46     ` SeungJu Cheon
2026-05-30 15:10   ` Jonathan Cameron
2026-05-31 10:49     ` SeungJu Cheon
2026-05-31 14:29       ` Jonathan Cameron
2026-05-30 11:39 ` [PATCH 2/4] iio: pressure: mpl3115: clean up interrupt handling and locking SeungJu Cheon
2026-05-30 12:33   ` Andy Shevchenko
2026-05-31 10:55     ` SeungJu Cheon
2026-05-30 15:23   ` Jonathan Cameron
2026-05-31 10:59     ` SeungJu Cheon
2026-05-30 11:39 ` [PATCH 3/4] iio: pressure: mpl3115: generalize interrupt pin routing SeungJu Cheon
2026-05-30 12:39   ` Andy Shevchenko
2026-05-31 11:01     ` SeungJu Cheon
2026-05-30 15:32   ` Jonathan Cameron [this message]
2026-05-31 11:08     ` SeungJu Cheon
2026-05-30 11:39 ` [PATCH 4/4] iio: pressure: mpl3115: add hardware FIFO support SeungJu Cheon
2026-05-30 13:32   ` Andy Shevchenko
2026-05-30 15:43     ` Jonathan Cameron
2026-06-02 10:31       ` Andy Shevchenko
2026-05-31 11:15     ` SeungJu Cheon
2026-05-30 16:05   ` Jonathan Cameron
2026-05-31 12:38     ` SeungJu Cheon

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260530163208.698e9b31@jic23-huawei \
    --to=jic23@kernel.org \
    --cc=andy@kernel.org \
    --cc=apokusinski01@gmail.com \
    --cc=dlechner@baylibre.com \
    --cc=linux-iio@vger.kernel.org \
    --cc=linux-kernel-mentees@lists.linux.dev \
    --cc=me@brighamcampbell.com \
    --cc=nuno.sa@analog.com \
    --cc=skhan@linuxfoundation.org \
    --cc=suunj1331@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox