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X-CSE-ConnectionGUID: 5twqriOERkySzpIrPUU3dg== X-CSE-MsgGUID: iKahw9H8QQGWLOKYis3Auw== X-IronPort-AV: E=McAfee;i="6800,10657,11508"; a="73765844" X-IronPort-AV: E=Sophos;i="6.17,254,1747724400"; d="scan'208";a="73765844" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2025 08:57:49 -0700 X-CSE-ConnectionGUID: 8cIJHB/3SUmlM0a4cX/yPQ== X-CSE-MsgGUID: XqtxjqHFRdi3S8nGUSXvgQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,254,1747724400"; d="scan'208";a="162575528" Received: from tfalcon-desk.amr.corp.intel.com (HELO [10.125.109.198]) ([10.125.109.198]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jul 2025 08:57:47 -0700 Message-ID: <3093fd14-d57a-4fc6-9e15-d9ce8b075b30@intel.com> Date: Thu, 31 Jul 2025 08:57:47 -0700 Precedence: bulk X-Mailing-List: linux-kernel-mentees@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] x86/cpu/intel: Fix the constant_tsc model check for Pentium 4s To: Suchit Karunakaran , tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, darwi@linutronix.de, sohil.mehta@intel.com, peterz@infradead.org, ravi.bangoria@amd.com Cc: skhan@linuxfoundation.org, linux-kernel-mentees@lists.linux.dev, linux-kernel@vger.kernel.org, stable@vger.kernel.org References: <20250730042617.5620-1-suchitkarunakaran@gmail.com> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 7/29/25 21:26, Suchit Karunakaran wrote: > The logic to synthesize constant_tsc for Pentium 4s (Family 15) is > wrong. Since INTEL_P4_PRESCOTT is numerically greater than > INTEL_P4_WILLAMETTE, the logic always results in false and never sets > X86_FEATURE_CONSTANT_TSC for any Pentium 4 model. > The error was introduced while replacing the x86_model check with a VFM > one. The original check was as follows: > if ((c->x86 == 0xf && c->x86_model >= 0x03) || > (c->x86 == 0x6 && c->x86_model >= 0x0e)) > set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); > > Fix the logic to cover all Pentium 4 models from Prescott (model 3) to > Cedarmill (model 6) which is the last model released in Family 15. Could we have a slightly different changelog, please? The fact that the logic results in the bit never getting set for P4's is IMNHO immaterial. This looks like a plain and simple typo, not a logical error on the patch author's part. How about this as a changelog? -- Pentium 4's which are INTEL_P4_PRESCOTT (mode 0x03) and later have a constant TSC. This was correctly captured until fadb6f569b10 ("x86/cpu/intel: Limit the non-architectural constant_tsc model checks"). In that commit, the model was transposed from 0x03 to INTEL_P4_WILLAMETTE, which is just plain wrong. That was presumably a simple typo, probably just copying and pasting the wrong P4 model. Fix the constant TSC logic to cover all later P4 models. End at INTEL_P4_CEDARMILL which is the last P4 model.