Re: [PATCH v3] x86/cpu/intel: Fix the constant_tsc model check for Pentium 4s

[Sohil Mehta <sohil.mehta@intel.com>]

On 7/31/2025 8:57 AM, Dave Hansen wrote:

> Could we have a slightly different changelog, please? The fact that the
> logic results in the bit never getting set for P4's is IMNHO immaterial.
> This looks like a plain and simple typo, not a logical error on the
> patch author's part.
> 

I can confirm it was a typing error that led to this bogus logic.

> How about this as a changelog?
> 

The changelog is fine, except the error happened while choosing the
upper bound (INTEL_P4_WILLAMETTE instead of INTEL_P4_CEDARMILL) and
*not* the lower bound (INTEL_P4_PRESCOTT) as suggested below.

> --
> 
> Pentium 4's which are INTEL_P4_PRESCOTT (mode 0x03) and later have a
> constant TSC. This was correctly captured until fadb6f569b10
> ("x86/cpu/intel: Limit the non-architectural constant_tsc model
> checks"). In that commit, the model was transposed from 0x03 to
> INTEL_P4_WILLAMETTE, which is just plain wrong. That was presumably a
> simple typo, probably just copying and pasting the wrong P4 model.
> 
> Fix the constant TSC logic to cover all later P4 models. End at
> INTEL_P4_CEDARMILL which is the last P4 model.

Tweaked this slightly for accuracy:

Pentium 4's which are INTEL_P4_PRESCOTT (model 0x03) and later have
a constant TSC. This was correctly captured until commit fadb6f569b10
("x86/cpu/intel: Limit the non-architectural constant_tsc model checks").

In that commit, an error was introduced while selecting the last P4
model (0x06) as the upper bound. Model 0x06 was transposed to
INTEL_P4_WILLAMETTE, which is just plain wrong. That was presumably a
simple typo, probably just copying and pasting the wrong P4 model.

Fix the constant TSC logic to cover all later P4 models. End at
INTEL_P4_CEDARMILL which accurately corresponds to the last P4 model.