From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from imap5.colo.codethink.co.uk (imap5.colo.codethink.co.uk [78.40.148.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 765E31E5B74; Fri, 4 Apr 2025 15:55:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=78.40.148.171 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743782134; cv=none; b=HV9x9HDPLAap80Ru82StLlX7RoeB5X0Qr708GHSl1X8AqrCQ0yAJH3umMviN54LrzCeUhEoeY1aKBJgMfB23bXkw2hW6aHRJvJGGBxp/1IfPGfXsh+zvPdxDFZ45tUGD764Kz/74lluBPTkSIQL4Ko9h93Iy7kw/y/405+IJRek= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743782134; c=relaxed/simple; bh=wbNKh+GG4KyPNqOJwVophT62W5B8u2ctwLCiSu+WSp4=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Rjm4ERGVoz9ZhSR8fk1Qm3kdQf24NaVlqXXmr11pEfFrQG3Mj6hEj7PFvY3E8fQ0WVRb6ykyJ3KD/eQ70zzu6jVsmUG+0A/puIOiRFcUePXtkDePjObcyZF+SUNLMseMP+FxQfia4WQYtzNMs8DuN4btwANP5+H707ZDt8Xr0NQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=codethink.co.uk; spf=pass smtp.mailfrom=codethink.co.uk; dkim=pass (2048-bit key) header.d=codethink.co.uk header.i=@codethink.co.uk header.b=JY/5IPL4; arc=none smtp.client-ip=78.40.148.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=codethink.co.uk Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=codethink.co.uk Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=codethink.co.uk header.i=@codethink.co.uk header.b="JY/5IPL4" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=codethink.co.uk; s=imap5-20230908; h=Sender:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=yOe9uz//SMDxuWVRWMVPDE6QGOnTyqzIEZ+QkHAgOCY=; b=JY/5IPL4YxFlzlOAZyBv1j4gvD caPYfIAA70Z4Q5WAnzFhgSjsLnLAjzLEIp34VTWCWGGAdeCWeHVgSq5RK/1QQNeC7iyhacimoNDRD BPw5Oq6kabuNQRfdygLdCkQfXNaY4jLf+TPvadMfDZ5lSaOAZKSH7+h4CJNeDzamrCvY6TzwYNN6x q3gnRJdpt7bJdil21IXtA0sJ/xtuOBwQ654633XpDuST+RlCrT3oGJqzEJLxjrkPd3ztXM+jBSJGq fSwBIpzsElIyaHuk8hf3Uvu4PWW0NffhPfumKWktV0PyXc0Wf6odDqdRiE7Py76vCwd+QvhSO/d6v TiTVtPVg==; Received: from [167.98.27.226] (helo=[10.35.6.194]) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1u0jO3-00BgMS-1f; Fri, 04 Apr 2025 16:55:20 +0100 Message-ID: <99b7b45a-4b18-4f0d-a197-4dccbb6c2352@codethink.co.uk> Date: Fri, 4 Apr 2025 16:55:19 +0100 Precedence: bulk X-Mailing-List: linux-kernel-mentees@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/2] riscv: introduce asm/swab.h To: Ignacio Encinas , Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Arnd Bergmann Cc: Eric Biggers , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linux.dev, skhan@linuxfoundation.org, Zhihang Shao , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , linux-arch@vger.kernel.org References: <20250403-riscv-swab-v3-0-3bf705d80e33@iencinas.com> <20250403-riscv-swab-v3-2-3bf705d80e33@iencinas.com> Content-Language: en-GB From: Ben Dooks Organization: Codethink Limited. In-Reply-To: <20250403-riscv-swab-v3-2-3bf705d80e33@iencinas.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Sender: ben.dooks@codethink.co.uk On 03/04/2025 21:34, Ignacio Encinas wrote: > Implement endianness swap macros for RISC-V. > > Use the rev8 instruction when Zbb is available. Otherwise, rely on the > default mask-and-shift implementation. > > Signed-off-by: Ignacio Encinas > --- > arch/riscv/include/asm/swab.h | 43 +++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 43 insertions(+) > > diff --git a/arch/riscv/include/asm/swab.h b/arch/riscv/include/asm/swab.h > new file mode 100644 > index 000000000000..7352e8405a99 > --- /dev/null > +++ b/arch/riscv/include/asm/swab.h > @@ -0,0 +1,43 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +#ifndef _ASM_RISCV_SWAB_H > +#define _ASM_RISCV_SWAB_H > + > +#include > +#include > +#include > +#include > +#include > + > +#if defined(CONFIG_RISCV_ISA_ZBB) && !defined(NO_ALTERNATIVE) > + > +#define ARCH_SWAB(size) \ > +static __always_inline unsigned long __arch_swab##size(__u##size value) \ > +{ \ > + unsigned long x = value; \ > + \ > + if (riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) { \ > + asm volatile (".option push\n" \ > + ".option arch,+zbb\n" \ > + "rev8 %0, %1\n" \ > + ".option pop\n" \ > + : "=r" (x) : "r" (x)); \ > + return x >> (BITS_PER_LONG - size); \ > + } \ > + return ___constant_swab##size(value); \ > +} > + > +#ifdef CONFIG_64BIT > +ARCH_SWAB(64) > +#define __arch_swab64 __arch_swab64 > +#endif I suppose if we're 64bit we can't just rely on values being in one register so this'd need special casing here? > +ARCH_SWAB(32) > +#define __arch_swab32 __arch_swab32 > + > +ARCH_SWAB(16) > +#define __arch_swab16 __arch_swab16 > + > +#undef ARCH_SWAB > + > +#endif /* defined(CONFIG_RISCV_ISA_ZBB) && !defined(NO_ALTERNATIVE) */ > +#endif /* _ASM_RISCV_SWAB_H */ > -- Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius https://www.codethink.co.uk/privacy.html