From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-187.mta1.migadu.com (out-187.mta1.migadu.com [95.215.58.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D25915DBB3 for ; Fri, 4 Apr 2025 18:13:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.187 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743790410; cv=none; b=MOPUA5SkOrN6d5FNCdwHr7EIoP6Z09EU3cAGdNEzOT3J+rR9munOq5WzOcoDI1QHVhD0J3yi/r8q60NRhi9xn193SBwd8LDgh+gnVufBu8++v6cNAr2237qCEwCSbcWNz91jDHozb65dI4Fmg5vHaR2lIY+ZtFGnxTMN8y56YFQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743790410; c=relaxed/simple; bh=18hN5x2RADFXLM5oIMb+dmlprtIX5ukfJpyHhTr93nE=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=UvBeHyKts5uwCJ3LkmdTblu6x+rWbWwDudvzm1/XYhfUFKV4bfawJRFQwZfPSPViYqFItJCaleElcvnuISSp9m9wxvUOrbbz0W7bjobxaBuQbs8JTCJRfFWTWJxY5Dvhw1p9T3BoeKGwsyujd4ThRFuxTbLWqGwhX/IQgZJAmbs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=iencinas.com; spf=pass smtp.mailfrom=iencinas.com; dkim=pass (2048-bit key) header.d=iencinas.com header.i=@iencinas.com header.b=X7/KzN87; arc=none smtp.client-ip=95.215.58.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=iencinas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iencinas.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=iencinas.com header.i=@iencinas.com header.b="X7/KzN87" Message-ID: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=iencinas.com; s=key1; t=1743790405; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uVNe9DB4JVS7mxluiBxcFesLyFlFXgqdxhl/MDOzqcY=; b=X7/KzN87/UO8MjCyQhAFLFpd4xU4Rssl/ezCIa3HYBH0BOtlU/YCJSSqcZERqRM4yKYu8A yMgGqdW/7vIuBTYE67LVQN6hxapbTAuWawGihHgrN8uS4frbqmiAK6cErBHgI2KNfm4r7m yiDIp6BGrDZj93AUpKiTQZJJWivU7jFr/DZTs3njv1dAgahFs4hmePYI8CumIlaU4G5gCZ NMENgUzoNCwqr612hNffJ/t8O42gPP1I/0yHjzl2xBQQArcDxfbBxEkL1+CiQ0GGzkhiP4 FCZypS8QGicnAUx90Gj93LPTSr4iGs/DsdNl4j0zDU7RtLVftfXntQv1lL4Hug== Date: Fri, 4 Apr 2025 20:13:17 +0200 Precedence: bulk X-Mailing-List: linux-kernel-mentees@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH v3 2/2] riscv: introduce asm/swab.h To: Ben Dooks , Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Arnd Bergmann Cc: Eric Biggers , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linux.dev, skhan@linuxfoundation.org, Zhihang Shao , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , linux-arch@vger.kernel.org References: <20250403-riscv-swab-v3-0-3bf705d80e33@iencinas.com> <20250403-riscv-swab-v3-2-3bf705d80e33@iencinas.com> <99b7b45a-4b18-4f0d-a197-4dccbb6c2352@codethink.co.uk> Content-Language: en-US X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Ignacio Encinas In-Reply-To: <99b7b45a-4b18-4f0d-a197-4dccbb6c2352@codethink.co.uk> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Migadu-Flow: FLOW_OUT On 4/4/25 17:55, Ben Dooks wrote: > On 03/04/2025 21:34, Ignacio Encinas wrote: >> +#ifdef CONFIG_64BIT >> +ARCH_SWAB(64) >> +#define __arch_swab64 __arch_swab64 >> +#endif > > I suppose if we're 64bit we can't just rely on values being in one > register so this'd need special casing here? Oops... I somehow decided that __arch_swab64 wasn't worth having for CONFIG_32BIT. I can't tell how useful it is to have it, but it is doable and already present in the codebase (include/uapi/linux/swab.h): __u32 h = val >> 32; __u32 l = val & ((1ULL << 32) - 1); return (((__u64)__fswab32(l)) << 32) | ((__u64)(__fswab32(h))); I'll excuse myself on this one because I'm not sure I have ever used a 32 bit CPU (other than the very occasional and quick school project) Thanks for catching this one! I'll make sure to add __arch_swab64 for the 32BIT version mimicking the snippet from above.