From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-178.mta1.migadu.com (out-178.mta1.migadu.com [95.215.58.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70A5322CBF8 for ; Fri, 21 Mar 2025 21:07:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.178 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742591270; cv=none; b=uDlQ6IAURkoBrQp8CwKqkciU634k3khZ/S1AOHpjwMQtbfyokWcooO8diwRxq8GYqK61AjCaaKyOD2n1sxjQKve/m1dzxqRUQecNkW8d/pBejcc0dyyYIDLNqnN1HhEbK4pcLfBWiJaNr/Oh5gnequNe8i+7hh7tTeO4RbcPdrc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742591270; c=relaxed/simple; bh=pRTN18mZjehBMY6cltsFf8sEbzCBSl3WgAjrrN95J08=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Xtt3CQl6ery41ad+GH5avbbRFtrqb8+mM3vtkMA+MsRFOKluxAjMkuGT/gNytG68ImaxQbMqQ2+1lfhVr8u2eg7Ah+N/Jfn+HVtBNDtyvZmQXNQudgzrrfslUmYYEc0miJ/HhDASnbbJsudv6qEE160+5EQOLnR0vSJXgraKdGU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=iencinas.com; spf=pass smtp.mailfrom=iencinas.com; dkim=pass (2048-bit key) header.d=iencinas.com header.i=@iencinas.com header.b=mxIWHDCe; arc=none smtp.client-ip=95.215.58.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=iencinas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iencinas.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=iencinas.com header.i=@iencinas.com header.b="mxIWHDCe" Message-ID: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=iencinas.com; s=key1; t=1742591266; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tlC6VNAA0VKAuMw2O3RagiC9hLYLd/5P5o/W8WtfpYs=; b=mxIWHDCeeOon6AofoQVDS+HDSKfYnVbPF754rvwIAwLC/90cv4eaY2l7cOOmH71p4z4pYd 3eb/sNdx0t06NJ6Uv2tnHtnP7ig3INMcIuHTY+GjKlFICWFi4gdK0pxJXanvDLMc7kxmIu WYCfKmw/2vvmgzkPVEOWRWMv3zdx5T9+nqqyL/0hgimAd77zQKiQMlMz7e2EzLfEnaxF8E CJhtGjidv1dnu83bXQXOaPz2SvRScNjw0/nZgHIa58dpHyTWxmCXc3zDdeOck9kezpPwPU Z8SR5t09thvptD8qA8BdOh+isZLwUBLvO9jsPbc83RG3UEXWlKwnC0wnBoX/zQ== Date: Fri, 21 Mar 2025 22:07:41 +0100 Precedence: bulk X-Mailing-List: linux-kernel-mentees@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH v2 2/2] riscv: introduce asm/swab.h To: Eric Biggers Cc: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Arnd Bergmann , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linux.dev, skhan@linuxfoundation.org, Zhihang Shao , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , linux-arch@vger.kernel.org References: <20250319-riscv-swab-v2-0-d53b6d6ab915@iencinas.com> <20250319-riscv-swab-v2-2-d53b6d6ab915@iencinas.com> <20250321033718.GA98513@sol.localdomain> Content-Language: en-US X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Ignacio Encinas Rubio In-Reply-To: <20250321033718.GA98513@sol.localdomain> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Migadu-Flow: FLOW_OUT On 21/3/25 4:37, Eric Biggers wrote: > On Wed, Mar 19, 2025 at 10:09:46PM +0100, Ignacio Encinas wrote: >> +#define ARCH_SWAB(size) \ >> +static __always_inline unsigned long __arch_swab##size(__u##size value) \ >> +{ \ >> + unsigned long x = value; \ >> + \ >> + asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, \ >> + RISCV_ISA_EXT_ZBB, 1) \ >> + :::: legacy); \ > > Is there a reason to use this instead of > riscv_has_extension_likely(RISCV_ISA_EXT_ZBB) which seems to do the same thing, > including using a static branch? I just followed what's already in arch/riscv/include/asm/bitops.h However, I changed it to if(riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) { asm volatile (".option push\n" ".option arch,+zbb\n" "rev8 %0, %1\n" ".option pop\n" : "=r" (x) : "r" (x)); return x >> (BITS_PER_LONG - size); } return ___constant_swab##size(value); and it seems gcc generates the exact same code. I tested it with arch/riscv/lib/csum.c (which uses swab32) and both versions generate the exact same object file. This certainly looks easier to read. If there are no complaints I'll send a v3 using a plain if with riscv_has_extension_likely. Thanks for pointing it out!