From: Ben Horgan <ben.horgan@arm.com>
To: Mark Brown <broonie@kernel.org>, Marc Zyngier <maz@kernel.org>,
Joey Gouly <joey.gouly@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Will Deacon <will@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>,
Oliver Upton <oupton@kernel.org>
Cc: Dave Martin <Dave.Martin@arm.com>, Fuad Tabba <tabba@google.com>,
Mark Rutland <mark.rutland@arm.com>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
Peter Maydell <peter.maydell@linaro.org>,
Eric Auger <eric.auger@redhat.com>
Subject: Re: [PATCH v10 28/30] KVM: arm64: selftests: Skip impossible invalid value tests
Date: Tue, 24 Mar 2026 14:54:54 +0000 [thread overview]
Message-ID: <0f8d0966-4e05-4d5a-a523-098b3dbcf7d9@arm.com> (raw)
In-Reply-To: <20260306-kvm-arm64-sme-v10-28-43f7683a0fb7@kernel.org>
Hi Mark,
On 3/6/26 17:01, Mark Brown wrote:
> The set_id_regs test currently assumes that there will always be invalid
> values available in bitfields for it to generate but this may not be the
> case if the architecture has defined meanings for every possible value for
> the bitfield. An assert added in commit bf09ee918053e ("KVM: arm64:
> selftests: Remove ARM64_FEATURE_FIELD_BITS and its last user") refuses to
> run for single bit fields which will show the issue most readily but there
> is no reason wider ones can't show the same issue.
>
> Rework the tests for invalid value to check if an invalid value can be
> generated and skip the test if not, removing the assert.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> tools/testing/selftests/kvm/arm64/set_id_regs.c | 63 +++++++++++++++++++++----
> 1 file changed, 53 insertions(+), 10 deletions(-)
>
> diff --git a/tools/testing/selftests/kvm/arm64/set_id_regs.c b/tools/testing/selftests/kvm/arm64/set_id_regs.c
> index bfca7be3e766..928e7d9e5ab7 100644
> --- a/tools/testing/selftests/kvm/arm64/set_id_regs.c
> +++ b/tools/testing/selftests/kvm/arm64/set_id_regs.c
> @@ -317,11 +317,12 @@ uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
> }
>
> /* Return an invalid value to a given ftr_bits an ftr value */
> -uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
> +uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr,
> + bool *skip)
> {
> uint64_t ftr_max = ftr_bits->mask >> ftr_bits->shift;
>
> - TEST_ASSERT(ftr_max > 1, "This test doesn't support single bit features");
> + *skip = false;
>
> if (ftr_bits->sign == FTR_UNSIGNED) {
> switch (ftr_bits->type) {
> @@ -329,42 +330,81 @@ uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
> ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
> break;
> case FTR_LOWER_SAFE:
> + if (ftr == ftr_max)
> + *skip = true;
> ftr++;
> break;
> case FTR_HIGHER_SAFE:
> + if (ftr == 0)
> + *skip = true;
> ftr--;
> break;
> case FTR_HIGHER_OR_ZERO_SAFE:
> - if (ftr == 0)
> + switch (ftr) {
> + case 0:
> ftr = ftr_max;
> - else
> + break;
> + case 1:
> + *skip = true;
> + break;
> + default:
> ftr--;
> + break;
> + }
> break;
> default:
> + *skip = true;
> break;
> }
> } else if (ftr != ftr_max) {
> switch (ftr_bits->type) {
> case FTR_EXACT:
> ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
> + if (ftr >= ftr_max)
> + *skip = true;
> break;
> case FTR_LOWER_SAFE:
> ftr++;
> break;
> case FTR_HIGHER_SAFE:
> - ftr--;
> + /* FIXME: "need to check for the actual highest." */
> + if (ftr == ftr_max)
> + *skip = true;
> + else
> + ftr--;
> break;
> case FTR_HIGHER_OR_ZERO_SAFE:
> - if (ftr == 0)
> - ftr = ftr_max - 1;
> - else
> + switch (ftr) {
> + case 0:
> + if (ftr_max > 1)
> + ftr = ftr_max - 1;
> + else
> + *skip = true;
> + break;
> + case 1:
> + *skip = true;
> + break;
> + default:
> ftr--;
> + break;
> + }
> break;
> default:
> + *skip = true;
> break;
> }
> } else {
> - ftr = 0;
> + switch (ftr_bits->type) {
> + case FTR_LOWER_SAFE:
> + if (ftr == 0)
> + *skip = true;
> + else
> + ftr = 0;
> + break;
> + default:
> + *skip = true;
> + break;
> + }
> }
I hacked up a quick loop to check what this function is doing.
With a mask=0x1 I see some value returned that have bits set
outside of the mask.
safe_val ftr out
UNSIGNED
FTR_EXACT
0x0 0x0 0x1
0x0 0x1 0x2 # out of range
0x1 0x0 0x2 # out of range
0x1 0x1 0x2 # out of range
FTR_LOWER_SAFE
0x0 0x0 0x1
0x0 0x1 SKIP
0x1 0x0 0x1
0x1 0x1 SKIP
FTR_HIGHER_SAFE
0x0 0x0 SKIP
0x0 0x1 0x0
0x1 0x0 SKIP
0x1 0x1 0x0
FTR_HIGHER_OR_ZERO_SAFE
0x0 0x0 0x1
0x0 0x1 SKIP
0x1 0x0 0x1
0x1 0x1 SKIP
SIGNED
FTR_EXACT
0x0 0x0 SKIP
0x0 0x1 SKIP
0x1 0x0 SKIP
0x1 0x1 SKIP
FTR_LOWER_SAFE
0x0 0x0 0x1
0x0 0x1 0x0
0x1 0x0 0x1
0x1 0x1 0x0
FTR_HIGHER_SAFE
0x0 0x0 0xffffffffffffffff # out of range
0x0 0x1 SKIP
0x1 0x0 0xffffffffffffffff # out of range
0x1 0x1 SKIP
FTR_HIGHER_OR_ZERO_SAFE
0x0 0x0 SKIP
0x0 0x1 SKIP
0x1 0x0 SKIP
0x1 0x1 SKIP
Thanks,
Ben
>
> return ftr;
> @@ -399,12 +439,15 @@ static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg,
> uint8_t shift = ftr_bits->shift;
> uint64_t mask = ftr_bits->mask;
> uint64_t val, old_val, ftr;
> + bool skip;
> int r;
>
> val = vcpu_get_reg(vcpu, reg);
> ftr = (val & mask) >> shift;
>
> - ftr = get_invalid_value(ftr_bits, ftr);
> + ftr = get_invalid_value(ftr_bits, ftr, &skip);
> + if (skip)
> + return;
>
> old_val = val;
> ftr <<= shift;
>
next prev parent reply other threads:[~2026-03-24 14:54 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-06 17:00 [PATCH v10 00/30] KVM: arm64: Implement support for SME Mark Brown
2026-03-06 17:00 ` [PATCH v10 01/30] arm64/sysreg: Update SMIDR_EL1 to DDI0601 2025-06 Mark Brown
2026-03-16 16:34 ` Catalin Marinas
2026-05-08 17:12 ` Mark Rutland
2026-05-09 0:43 ` Mark Brown
2026-03-06 17:00 ` [PATCH v10 02/30] arm64/fpsimd: Update FA64 and ZT0 enables when loading SME state Mark Brown
2026-03-16 17:37 ` Catalin Marinas
2026-03-06 17:00 ` [PATCH v10 03/30] arm64/fpsimd: Decide to save ZT0 and streaming mode FFR at bind time Mark Brown
2026-03-16 17:42 ` Catalin Marinas
2026-03-06 17:00 ` [PATCH v10 04/30] arm64/fpsimd: Determine maximum virtualisable SME vector length Mark Brown
2026-03-16 17:44 ` Catalin Marinas
2026-03-18 17:29 ` Jean-Philippe Brucker
2026-03-06 17:00 ` [PATCH v10 05/30] KVM: arm64: Pay attention to FFR parameter in SVE save and load Mark Brown
2026-03-18 17:30 ` Jean-Philippe Brucker
2026-03-06 17:00 ` [PATCH v10 06/30] KVM: arm64: Pull ctxt_has_ helpers to start of sysreg-sr.h Mark Brown
2026-03-18 17:31 ` Jean-Philippe Brucker
2026-03-06 17:00 ` [PATCH v10 07/30] KVM: arm64: Move SVE state access macros after feature test macros Mark Brown
2026-03-18 17:32 ` Jean-Philippe Brucker
2026-03-06 17:01 ` [PATCH v10 08/30] KVM: arm64: Rename SVE finalization constants to be more general Mark Brown
2026-03-18 17:33 ` Jean-Philippe Brucker
2026-03-06 17:01 ` [PATCH v10 09/30] KVM: arm64: Define internal features for SME Mark Brown
2026-03-18 17:44 ` Jean-Philippe Brucker
2026-03-18 17:50 ` Mark Brown
2026-03-06 17:01 ` [PATCH v10 10/30] KVM: arm64: Rename sve_state_reg_region Mark Brown
2026-03-18 17:46 ` Jean-Philippe Brucker
2026-03-06 17:01 ` [PATCH v10 11/30] KVM: arm64: Store vector lengths in an array Mark Brown
2026-03-18 17:48 ` Jean-Philippe Brucker
2026-03-06 17:01 ` [PATCH v10 12/30] KVM: arm64: Factor SVE code out of fpsimd_lazy_switch_to_host() Mark Brown
2026-03-18 17:49 ` Jean-Philippe Brucker
2026-03-06 17:01 ` [PATCH v10 13/30] KVM: arm64: Document the KVM ABI for SME Mark Brown
2026-03-18 17:51 ` Jean-Philippe Brucker
2026-03-06 17:01 ` [PATCH v10 14/30] KVM: arm64: Implement SME vector length configuration Mark Brown
2026-03-18 17:53 ` Jean-Philippe Brucker
2026-04-23 18:34 ` Mark Brown
2026-03-06 17:01 ` [PATCH v10 15/30] KVM: arm64: Support SME control registers Mark Brown
2026-03-18 17:54 ` Jean-Philippe Brucker
2026-05-08 17:20 ` Mark Rutland
2026-03-06 17:01 ` [PATCH v10 16/30] KVM: arm64: Support TPIDR2_EL0 Mark Brown
2026-03-18 17:55 ` Jean-Philippe Brucker
2026-03-06 17:01 ` [PATCH v10 17/30] KVM: arm64: Support SME identification registers for guests Mark Brown
2026-03-18 17:27 ` Jean-Philippe Brucker
2026-03-06 17:01 ` [PATCH v10 18/30] KVM: arm64: Support SME priority registers Mark Brown
2026-03-06 17:01 ` [PATCH v10 19/30] KVM: arm64: Provide assembly for SME register access Mark Brown
2026-03-06 17:01 ` [PATCH v10 20/30] KVM: arm64: Support userspace access to streaming mode Z and P registers Mark Brown
2026-03-06 17:01 ` [PATCH v10 21/30] KVM: arm64: Flush register state on writes to SVCR.SM and SVCR.ZA Mark Brown
2026-03-06 17:01 ` [PATCH v10 22/30] KVM: arm64: Expose SME specific state to userspace Mark Brown
2026-03-06 17:01 ` [PATCH v10 23/30] KVM: arm64: Context switch SME state for guests Mark Brown
2026-03-06 17:01 ` [PATCH v10 24/30] KVM: arm64: Handle SME exceptions Mark Brown
2026-03-06 17:01 ` [PATCH v10 25/30] KVM: arm64: Expose SME to nested guests Mark Brown
2026-03-06 17:01 ` [PATCH v10 26/30] KVM: arm64: Provide interface for configuring and enabling SME for guests Mark Brown
2026-03-06 17:01 ` [PATCH v10 27/30] KVM: arm64: selftests: Remove spurious check for single bit safe values Mark Brown
2026-03-06 17:01 ` [PATCH v10 28/30] KVM: arm64: selftests: Skip impossible invalid value tests Mark Brown
2026-03-24 14:54 ` Ben Horgan [this message]
2026-03-24 14:56 ` Mark Brown
2026-03-06 17:01 ` [PATCH v10 29/30] KVM: arm64: selftests: Add SME system registers to get-reg-list Mark Brown
2026-03-06 17:01 ` [PATCH v10 30/30] KVM: arm64: selftests: Add SME to set_id_regs test Mark Brown
2026-04-02 21:12 ` (subset) [PATCH v10 00/30] KVM: arm64: Implement support for SME Catalin Marinas
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