From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2D61C31E5B for ; Mon, 17 Jun 2019 15:23:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 834CC208E4 for ; Mon, 17 Jun 2019 15:23:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=efficios.com header.i=@efficios.com header.b="XUfSTY7i" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726331AbfFQPXV (ORCPT ); Mon, 17 Jun 2019 11:23:21 -0400 Received: from mail.efficios.com ([167.114.142.138]:49246 "EHLO mail.efficios.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726731AbfFQPXV (ORCPT ); Mon, 17 Jun 2019 11:23:21 -0400 Received: from localhost (ip6-localhost [IPv6:::1]) by mail.efficios.com (Postfix) with ESMTP id 826181D3299; Mon, 17 Jun 2019 11:23:19 -0400 (EDT) Received: from mail.efficios.com ([IPv6:::1]) by localhost (mail02.efficios.com [IPv6:::1]) (amavisd-new, port 10032) with ESMTP id ngNwKsoUCGaa; Mon, 17 Jun 2019 11:23:19 -0400 (EDT) Received: from localhost (ip6-localhost [IPv6:::1]) by mail.efficios.com (Postfix) with ESMTP id EE5031D3296; Mon, 17 Jun 2019 11:23:18 -0400 (EDT) DKIM-Filter: OpenDKIM Filter v2.10.3 mail.efficios.com EE5031D3296 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=efficios.com; s=default; t=1560784999; bh=f6zEYKJAJi61hi21J79TEKs+00z096e7T6EdDgLZ27Q=; h=From:To:Date:Message-Id; b=XUfSTY7iw/fxGCimF720oI0UhmPxVmZr0fed4jAc6D0gpqwoyfmz/Cwdohyvv/Hm2 y6PMBYLiVQ8f/wDBthKLFyVvTG8sbCkTX9TBdZEaTT992gFU3Di082S30pv6t2wXJi umbT3GGplzzGAxcu5tCOM0tw0waBdnivsaWvyIhSisWysalMqcYYMvOg6f+ndVje5q VrWzzpTooBDGyo7nrHsXcIDlNeqgo7xQaRFKCZ1Q5ftx7cbXsDoUb34kR3Esax76OI I3RF37qUbredmBKubaVKwjbIp0bF0aiL7gDknaLY9IPWqMKxjJu1SJg0gW9aSBa7SZ hkIPnRV2GTO0g== X-Virus-Scanned: amavisd-new at efficios.com Received: from mail.efficios.com ([IPv6:::1]) by localhost (mail02.efficios.com [IPv6:::1]) (amavisd-new, port 10026) with ESMTP id NWfrek6MexdY; Mon, 17 Jun 2019 11:23:18 -0400 (EDT) Received: from thinkos.internal.efficios.com (192-222-181-218.qc.cable.ebox.net [192.222.181.218]) by mail.efficios.com (Postfix) with ESMTPSA id 61ADB1D3291; Mon, 17 Jun 2019 11:23:18 -0400 (EDT) From: Mathieu Desnoyers To: Shuah Khan , Will Deacon Cc: linux-kernel@vger.kernel.org, Mathieu Desnoyers , Peter Zijlstra , Thomas Gleixner , Joel Fernandes , Catalin Marinas , Dave Watson , Andi Kleen , linux-kselftest@vger.kernel.org, "H . Peter Anvin" , Chris Lameter , Russell King , Michael Kerrisk , "Paul E . McKenney" , Paul Turner , Boqun Feng , Josh Triplett , Steven Rostedt , Ben Maurer , linux-api@vger.kernel.org, Andy Lutomirski , Andrew Morton , Linus Torvalds , Carlos O'Donell , Florian Weimer Subject: [RFC PATCH 1/1] Revert "rseq/selftests: arm: use udf instruction for RSEQ_SIG" Date: Mon, 17 Jun 2019 17:23:04 +0200 Message-Id: <20190617152304.23371-1-mathieu.desnoyers@efficios.com> X-Mailer: git-send-email 2.11.0 Sender: linux-kselftest-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org This reverts commit 2b845d4b4acd9422bbb668989db8dc36dfc8f438. That commit introduces build issues for programs compiled in Thumb mode. Rather than try to be clever and emit a valid trap instruction on arm32, which requires special care about big/little endian handling on that architecture, just emit plain data. Data in the instruction stream is technically expected on arm32: this is how literal pools are implemented. Reverting to the prior behavior does exactly that. Signed-off-by: Mathieu Desnoyers CC: Peter Zijlstra CC: Thomas Gleixner CC: Joel Fernandes CC: Catalin Marinas CC: Dave Watson CC: Will Deacon CC: Shuah Khan CC: Andi Kleen CC: linux-kselftest@vger.kernel.org CC: "H . Peter Anvin" CC: Chris Lameter CC: Russell King CC: Michael Kerrisk CC: "Paul E . McKenney" CC: Paul Turner CC: Boqun Feng CC: Josh Triplett CC: Steven Rostedt CC: Ben Maurer CC: linux-api@vger.kernel.org CC: Andy Lutomirski CC: Andrew Morton CC: Linus Torvalds CC: Carlos O'Donell CC: Florian Weimer --- tools/testing/selftests/rseq/rseq-arm.h | 52 ++------------------------------- 1 file changed, 2 insertions(+), 50 deletions(-) diff --git a/tools/testing/selftests/rseq/rseq-arm.h b/tools/testing/selftests/rseq/rseq-arm.h index 84f28f147fb6..5f262c54364f 100644 --- a/tools/testing/selftests/rseq/rseq-arm.h +++ b/tools/testing/selftests/rseq/rseq-arm.h @@ -5,54 +5,7 @@ * (C) Copyright 2016-2018 - Mathieu Desnoyers */ -/* - * RSEQ_SIG uses the udf A32 instruction with an uncommon immediate operand - * value 0x5de3. This traps if user-space reaches this instruction by mistake, - * and the uncommon operand ensures the kernel does not move the instruction - * pointer to attacker-controlled code on rseq abort. - * - * The instruction pattern in the A32 instruction set is: - * - * e7f5def3 udf #24035 ; 0x5de3 - * - * This translates to the following instruction pattern in the T16 instruction - * set: - * - * little endian: - * def3 udf #243 ; 0xf3 - * e7f5 b.n <7f5> - * - * pre-ARMv6 big endian code: - * e7f5 b.n <7f5> - * def3 udf #243 ; 0xf3 - * - * ARMv6+ -mbig-endian generates mixed endianness code vs data: little-endian - * code and big-endian data. Ensure the RSEQ_SIG data signature matches code - * endianness. Prior to ARMv6, -mbig-endian generates big-endian code and data - * (which match), so there is no need to reverse the endianness of the data - * representation of the signature. However, the choice between BE32 and BE8 - * is done by the linker, so we cannot know whether code and data endianness - * will be mixed before the linker is invoked. - */ - -#define RSEQ_SIG_CODE 0xe7f5def3 - -#ifndef __ASSEMBLER__ - -#define RSEQ_SIG_DATA \ - ({ \ - int sig; \ - asm volatile ("b 2f\n\t" \ - "1: .inst " __rseq_str(RSEQ_SIG_CODE) "\n\t" \ - "2:\n\t" \ - "ldr %[sig], 1b\n\t" \ - : [sig] "=r" (sig)); \ - sig; \ - }) - -#define RSEQ_SIG RSEQ_SIG_DATA - -#endif +#define RSEQ_SIG 0x53053053 #define rseq_smp_mb() __asm__ __volatile__ ("dmb" ::: "memory", "cc") #define rseq_smp_rmb() __asm__ __volatile__ ("dmb" ::: "memory", "cc") @@ -125,8 +78,7 @@ do { \ __rseq_str(table_label) ":\n\t" \ ".word " __rseq_str(version) ", " __rseq_str(flags) "\n\t" \ ".word " __rseq_str(start_ip) ", 0x0, " __rseq_str(post_commit_offset) ", 0x0, " __rseq_str(abort_ip) ", 0x0\n\t" \ - ".arm\n\t" \ - ".inst " __rseq_str(RSEQ_SIG_CODE) "\n\t" \ + ".word " __rseq_str(RSEQ_SIG) "\n\t" \ __rseq_str(label) ":\n\t" \ teardown \ "b %l[" __rseq_str(abort_label) "]\n\t" -- 2.11.0