From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Shuah Khan <skhan@linuxfoundation.org>,
Shuah Khan <shuah@kernel.org>
Cc: Alan Hayward <alan.hayward@arm.com>,
Luis Machado <luis.machado@arm.com>,
Szabolcs Nagy <szabolcs.nagy@arm.com>,
linux-arm-kernel@lists.infradead.org,
linux-kselftest@vger.kernel.org, Mark Brown <broonie@kernel.org>
Subject: [PATCH v2 02/21] arm64: Document boot requirements for SME 2
Date: Tue, 1 Nov 2022 14:33:17 +0000 [thread overview]
Message-ID: <20221101143336.254445-3-broonie@kernel.org> (raw)
In-Reply-To: <20221101143336.254445-1-broonie@kernel.org>
SME 2 introduces the new ZT0 register, we require that access to this
reigster is not trapped when we identify that the feature is supported.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/arm64/booting.rst | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
index 8aefa1001ae5..b69b5cb596e6 100644
--- a/Documentation/arm64/booting.rst
+++ b/Documentation/arm64/booting.rst
@@ -360,6 +360,16 @@ Before jumping into the kernel, the following conditions must be met:
- HCR_EL2.ATA (bit 56) must be initialised to 0b1.
+ For CPUs with the Scalable Matrix Extension version 2 (FEAT_SME2):
+
+ - If EL3 is present:
+
+ - SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1.
+
+ - If the kernel is entered at EL1 and EL2 is present:
+
+ - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.
+
The requirements described above for CPU mode, caches, MMUs, architected
timers, coherency and system registers apply to all CPUs. All CPUs must
enter the kernel in the same exception level. Where the values documented
--
2.30.2
next prev parent reply other threads:[~2022-11-01 14:39 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-01 14:33 [PATCH v2 00/21] arm64/sme: Support SME 2 and SME 2.1 Mark Brown
2022-11-01 14:33 ` [PATCH v2 01/21] arm64/sme: Rename za_state to sme_state Mark Brown
2022-11-01 14:33 ` Mark Brown [this message]
2022-11-01 14:33 ` [PATCH v2 03/21] arm64/sysreg: Update system registers for SME 2 and 2.1 Mark Brown
2022-11-01 14:33 ` [PATCH v2 04/21] arm64/sme: Document SME 2 and SME 2.1 ABI Mark Brown
2022-11-11 10:17 ` Luis Machado
2022-11-11 10:38 ` Luis Machado
2022-11-11 11:20 ` Mark Brown
2022-11-01 14:33 ` [PATCH v2 05/21] arm64/esr: Document ISS for ZT0 being disabled Mark Brown
2022-11-01 14:33 ` [PATCH v2 06/21] arm64/sme: Manually encode ZT0 load and store instructions Mark Brown
2022-11-01 14:33 ` [PATCH v2 07/21] arm64/sme: Enable host kernel to access ZT0 Mark Brown
2022-11-01 14:33 ` [PATCH v2 08/21] arm64/sme: Add basic enumeration for SME2 Mark Brown
2022-11-01 14:33 ` [PATCH v2 09/21] arm64/sme: Provide storage for ZT0 Mark Brown
2022-11-01 14:33 ` [PATCH v2 10/21] arm64/sme: Implement context switching " Mark Brown
2022-11-01 14:33 ` [PATCH v2 11/21] arm64/sme: Implement signal handling for ZT Mark Brown
2022-11-01 14:33 ` [PATCH v2 12/21] arm64/sme: Implement ZT0 ptrace support Mark Brown
2022-11-11 10:31 ` Luis Machado
2022-11-11 11:25 ` Mark Brown
2022-11-01 14:33 ` [PATCH v2 13/21] arm64/sme: Add hwcaps for SME 2 and 2.1 features Mark Brown
2022-11-01 14:33 ` [PATCH v2 14/21] kselftest/arm64: Add a stress test program for ZT0 Mark Brown
2022-11-01 14:33 ` [PATCH v2 15/21] kselftest/arm64: Cover ZT in the FP stress test Mark Brown
2022-11-01 14:33 ` [PATCH v2 16/21] kselftest/arm64: Enumerate SME2 in the signal test utility code Mark Brown
2022-11-01 14:33 ` [PATCH v2 17/21] kselftest/arm64: Teach the generic signal context validation about ZT Mark Brown
2022-11-01 14:33 ` [PATCH v2 18/21] kselftest/arm64: Add test coverage for ZT register signal frames Mark Brown
2022-11-01 14:33 ` [PATCH v2 19/21] kselftest/arm64: Add SME2 coverage to syscall-abi Mark Brown
2022-11-01 14:33 ` [PATCH v2 20/21] kselftest/arm64: Add coverage of the ZT ptrace regset Mark Brown
2022-11-01 14:33 ` [PATCH v2 21/21] kselftest/arm64: Add coverage of SME 2 and 2.1 hwcaps Mark Brown
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221101143336.254445-3-broonie@kernel.org \
--to=broonie@kernel.org \
--cc=alan.hayward@arm.com \
--cc=catalin.marinas@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kselftest@vger.kernel.org \
--cc=luis.machado@arm.com \
--cc=shuah@kernel.org \
--cc=skhan@linuxfoundation.org \
--cc=szabolcs.nagy@arm.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox