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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id m16-20020a05600c4f5000b0040c57e4ea28sm4720420wmq.17.2023.12.13.09.36.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 09:36:24 -0800 (PST) Date: Wed, 13 Dec 2023 18:36:23 +0100 From: Andrew Jones To: Anup Patel Cc: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Shuah Khan , Anup Patel , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH 04/15] RISC-V: KVM: Allow scalar crypto extensions for Guest/VM Message-ID: <20231213-1c93d927d30feb6d09739e94@orel> References: <20231128145357.413321-1-apatel@ventanamicro.com> <20231128145357.413321-5-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231128145357.413321-5-apatel@ventanamicro.com> On Tue, Nov 28, 2023 at 08:23:46PM +0530, Anup Patel wrote: > We extend the KVM ISA extension ONE_REG interface to allow KVM > user space to detect and enable scalar crypto extensions for > Guest/VM. This includes extensions Zbkb, Zbkc, Zbkx, Zknd, Zkne, > Zknh, Zkr, Zksed, Zksh, and Zkt. > > Signed-off-by: Anup Patel > --- > arch/riscv/include/uapi/asm/kvm.h | 10 ++++++++++ > arch/riscv/kvm/vcpu_onereg.c | 20 ++++++++++++++++++++ > 2 files changed, 30 insertions(+) > > diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h > index 518b368b41e5..7b54fa215d6d 100644 > --- a/arch/riscv/include/uapi/asm/kvm.h > +++ b/arch/riscv/include/uapi/asm/kvm.h > @@ -140,6 +140,16 @@ enum KVM_RISCV_ISA_EXT_ID { > KVM_RISCV_ISA_EXT_SMSTATEEN, > KVM_RISCV_ISA_EXT_ZICOND, > KVM_RISCV_ISA_EXT_ZBC, > + KVM_RISCV_ISA_EXT_ZBKB, > + KVM_RISCV_ISA_EXT_ZBKC, > + KVM_RISCV_ISA_EXT_ZBKX, > + KVM_RISCV_ISA_EXT_ZKND, > + KVM_RISCV_ISA_EXT_ZKNE, > + KVM_RISCV_ISA_EXT_ZKNH, > + KVM_RISCV_ISA_EXT_ZKR, > + KVM_RISCV_ISA_EXT_ZKSED, > + KVM_RISCV_ISA_EXT_ZKSH, > + KVM_RISCV_ISA_EXT_ZKT, > KVM_RISCV_ISA_EXT_MAX, > }; > > diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c > index f789517c9fae..b0beebd4f86e 100644 > --- a/arch/riscv/kvm/vcpu_onereg.c > +++ b/arch/riscv/kvm/vcpu_onereg.c > @@ -43,6 +43,9 @@ static const unsigned long kvm_isa_ext_arr[] = { > KVM_ISA_EXT_ARR(ZBA), > KVM_ISA_EXT_ARR(ZBB), > KVM_ISA_EXT_ARR(ZBC), > + KVM_ISA_EXT_ARR(ZBKB), > + KVM_ISA_EXT_ARR(ZBKC), > + KVM_ISA_EXT_ARR(ZBKX), > KVM_ISA_EXT_ARR(ZBS), > KVM_ISA_EXT_ARR(ZICBOM), > KVM_ISA_EXT_ARR(ZICBOZ), > @@ -52,6 +55,13 @@ static const unsigned long kvm_isa_ext_arr[] = { > KVM_ISA_EXT_ARR(ZIFENCEI), > KVM_ISA_EXT_ARR(ZIHINTPAUSE), > KVM_ISA_EXT_ARR(ZIHPM), > + KVM_ISA_EXT_ARR(ZKND), > + KVM_ISA_EXT_ARR(ZKNE), > + KVM_ISA_EXT_ARR(ZKNH), > + KVM_ISA_EXT_ARR(ZKR), > + KVM_ISA_EXT_ARR(ZKSED), > + KVM_ISA_EXT_ARR(ZKSH), > + KVM_ISA_EXT_ARR(ZKT), > }; > > static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext) > @@ -94,6 +104,9 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) > case KVM_RISCV_ISA_EXT_ZBA: > case KVM_RISCV_ISA_EXT_ZBB: > case KVM_RISCV_ISA_EXT_ZBC: > + case KVM_RISCV_ISA_EXT_ZBKB: > + case KVM_RISCV_ISA_EXT_ZBKC: > + case KVM_RISCV_ISA_EXT_ZBKX: > case KVM_RISCV_ISA_EXT_ZBS: > case KVM_RISCV_ISA_EXT_ZICNTR: > case KVM_RISCV_ISA_EXT_ZICOND: > @@ -101,6 +114,13 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) > case KVM_RISCV_ISA_EXT_ZIFENCEI: > case KVM_RISCV_ISA_EXT_ZIHINTPAUSE: > case KVM_RISCV_ISA_EXT_ZIHPM: > + case KVM_RISCV_ISA_EXT_ZKND: > + case KVM_RISCV_ISA_EXT_ZKNE: > + case KVM_RISCV_ISA_EXT_ZKNH: > + case KVM_RISCV_ISA_EXT_ZKR: > + case KVM_RISCV_ISA_EXT_ZKSED: > + case KVM_RISCV_ISA_EXT_ZKSH: > + case KVM_RISCV_ISA_EXT_ZKT: > return false; > /* Extensions which can be disabled using Smstateen */ > case KVM_RISCV_ISA_EXT_SSAIA: > -- > 2.34.1 > Reviewed-by: Andrew Jones