From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="cqna6UjT" Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 568ED121 for ; Wed, 13 Dec 2023 06:02:54 -0800 (PST) Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-40c2bb872e2so65104005e9.3 for ; Wed, 13 Dec 2023 06:02:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1702476173; x=1703080973; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=W8CNgTMGbobolB1r9w8VNb165BlBAplPuvdaxYrWog0=; b=cqna6UjTYgeJ8FSvk+RW1RP2hFvImNPYN83jAtbXOkXJaaksS/kR0sg96ap1082BKz p38ZcoACnlhalY9oCt9dN7rZhZa8OLQl0WdCTDIjA2myxB9XkFsY5tvdBeNIsvNf929d 2bHGlm4E8SZWSXGjCd2Vf9vCNHc2X5LXyTgmCN20k7IQ9ihxzMwZBTsIf1IF8Cu42b3w QMvYW5BRq+cDMcsF+JLCeeFnBGZeyeYUMgkRfjtstVMlvMpnBK8ncqFkw9e8o5WI7bas dB3CLtU/QVU64DFhNif9pTGGCu885Ln8G8pOFNuIr5ueW3o+4frxFeVFfufN+vrVh8hX xlhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702476173; x=1703080973; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=W8CNgTMGbobolB1r9w8VNb165BlBAplPuvdaxYrWog0=; b=R46/MhTTnboObDzUJ4nlSSymV3kpSfIC3CW7+ZQW6w/oBzJgvM0FTciaVVXwjwRyRv RXyxQEoNEeQQ7kj9UTg9Z9RUoSnEcjXlnn59hYZQBw5Xa5CgWuv5AIyPYHTbKr9gEOlL krJLsmAihklbyB+Jknqwpa9JDWH3Dm8/8AZTQmqfLci2/RGyEsTy8jJp4qg0TiSP29a+ UbOfYbQys8PND8l/lNbuGqe9RgCSmbaeTUVacrVcn3TFtW2QN62aceo1dQaNQUIII0cU fN5kqeGzS5wrSEe4Oo+jSdvh23UjPPBJ4mF8E7GccuIxedRNM3/iSybzue7brif9MxZY yxGg== X-Gm-Message-State: AOJu0YxYd05lehitWepUJEpxJmTeW/zV+QpH38plIclGZTF7fesV44B5 B2We4JiAKBMWJ9C8uCymU1JVOA== X-Google-Smtp-Source: AGHT+IHHe1VYvYeZf/3ceduRCoWvVbIdH20JSg3fNMXtxhw7fHkTGIiZ2b27mL7MboW3CuD0I846lA== X-Received: by 2002:a05:600c:2483:b0:40c:3314:5be0 with SMTP id 3-20020a05600c248300b0040c33145be0mr1879277wms.295.1702476172702; Wed, 13 Dec 2023 06:02:52 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id fm14-20020a05600c0c0e00b00407b93d8085sm22968185wmb.27.2023.12.13.06.02.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 06:02:52 -0800 (PST) Date: Wed, 13 Dec 2023 15:02:51 +0100 From: Andrew Jones To: Haibo Xu Cc: xiaobo55x@gmail.com, Paul Walmsley , Palmer Dabbelt , Albert Ou , Paolo Bonzini , Shuah Khan , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Anup Patel , Atish Patra , Guo Ren , Conor Dooley , Mayuresh Chitale , Daniel Henrique Barboza , Jisheng Zhang , Samuel Holland , Minda Chen , Sean Christopherson , Peter Xu , Like Xu , Vipin Sharma , Maciej Wieczor-Retman , Thomas Huth , Aaron Lewis , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm-riscv@lists.infradead.org Subject: Re: [PATCH v4 05/11] tools: riscv: Add header file vdso/processor.h Message-ID: <20231213-9d5ad03bed3056007c6e714d@orel> References: <7b633cc441f5133608597463301fef122f5174d3.1702371136.git.haibo1.xu@intel.com> Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <7b633cc441f5133608597463301fef122f5174d3.1702371136.git.haibo1.xu@intel.com> On Tue, Dec 12, 2023 at 05:31:14PM +0800, Haibo Xu wrote: > Borrow the cpu_relax() definitions from kernel's > arch/riscv/include/asm/vdso/processor.h to tools/ for riscv. > > Signed-off-by: Haibo Xu > --- > tools/arch/riscv/include/asm/vdso/processor.h | 32 +++++++++++++++++++ > 1 file changed, 32 insertions(+) > create mode 100644 tools/arch/riscv/include/asm/vdso/processor.h > > diff --git a/tools/arch/riscv/include/asm/vdso/processor.h b/tools/arch/riscv/include/asm/vdso/processor.h > new file mode 100644 > index 000000000000..662aca039848 > --- /dev/null > +++ b/tools/arch/riscv/include/asm/vdso/processor.h > @@ -0,0 +1,32 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +#ifndef __ASM_VDSO_PROCESSOR_H > +#define __ASM_VDSO_PROCESSOR_H > + > +#ifndef __ASSEMBLY__ > + > +#include > + > +static inline void cpu_relax(void) > +{ > +#ifdef __riscv_muldiv > + int dummy; > + /* In lieu of a halt instruction, induce a long-latency stall. */ > + __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy)); > +#endif > + > +#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE > + /* > + * Reduce instruction retirement. > + * This assumes the PC changes. > + */ > + __asm__ __volatile__ ("pause"); > +#else > + /* Encoding of the pause instruction */ > + __asm__ __volatile__ (".4byte 0x100000F"); > +#endif > + barrier(); > +} > + > +#endif /* __ASSEMBLY__ */ > + > +#endif /* __ASM_VDSO_PROCESSOR_H */ > -- > 2.34.1 > Reviewed-by: Andrew Jones