Re: [PATCH v5 01/22] RISC-V: Fix the typo in Scountovf CSR name

Andrew Jones
2024-04-04T10:56:39Z

On Wed, Apr 03, 2024 at 01:04:30AM -0700, Atish Patra wrote:
> The counter overflow CSR name is "scountovf" not "sscountovf".
>
> Fix the csr name.
>
> Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support")
> Reviewed-by: Clément Léger <cleger@rivosinc.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
> arch/riscv/include/asm/csr.h | 2 +-
> drivers/perf/riscv_pmu_sbi.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index 2468c55933cd..9d1b07932794 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -281,7 +281,7 @@
> #define CSR_HPMCOUNTER30H 0xc9e
> #define CSR_HPMCOUNTER31H 0xc9f
>
> -#define CSR_SSCOUNTOVF 0xda0
> +#define CSR_SCOUNTOVF 0xda0
>
> #define CSR_SSTATUS 0x100
> #define CSR_SIE 0x104
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index 8cbe6e5f9c39..3e44d2fb8bf8 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -27,7 +27,7 @@
>
> #define ALT_SBI_PMU_OVERFLOW(__ovl) \
> asm volatile(ALTERNATIVE_2( \
> - "csrr %0, " __stringify(CSR_SSCOUNTOVF), \
> + "csrr %0, " __stringify(CSR_SCOUNTOVF), \
> "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \
> THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \
> CONFIG_ERRATA_THEAD_PMU, \
> --
> 2.34.1
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>