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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id f10-20020a0560001b0a00b00341dbb4a3a7sm19705617wrz.86.2024.04.04.03.56.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Apr 2024 03:56:37 -0700 (PDT) Date: Thu, 4 Apr 2024 12:56:36 +0200 From: Andrew Jones To: Atish Patra Cc: linux-kernel@vger.kernel.org, =?utf-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= , Conor Dooley , Anup Patel , Ajay Kaher , Alexandre Ghiti , Alexey Makhalov , Juergen Gross , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Shuah Khan , virtualization@lists.linux.dev, VMware PV-Drivers Reviewers , Will Deacon , x86@kernel.org Subject: Re: [PATCH v5 01/22] RISC-V: Fix the typo in Scountovf CSR name Message-ID: <20240404-9c750d13d89168feb5ff34de@orel> References: <20240403080452.1007601-1-atishp@rivosinc.com> <20240403080452.1007601-2-atishp@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240403080452.1007601-2-atishp@rivosinc.com> On Wed, Apr 03, 2024 at 01:04:30AM -0700, Atish Patra wrote: > The counter overflow CSR name is "scountovf" not "sscountovf". > > Fix the csr name. > > Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") > Reviewed-by: Clément Léger > Reviewed-by: Conor Dooley > Reviewed-by: Anup Patel > Signed-off-by: Atish Patra > --- > arch/riscv/include/asm/csr.h | 2 +- > drivers/perf/riscv_pmu_sbi.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > index 2468c55933cd..9d1b07932794 100644 > --- a/arch/riscv/include/asm/csr.h > +++ b/arch/riscv/include/asm/csr.h > @@ -281,7 +281,7 @@ > #define CSR_HPMCOUNTER30H 0xc9e > #define CSR_HPMCOUNTER31H 0xc9f > > -#define CSR_SSCOUNTOVF 0xda0 > +#define CSR_SCOUNTOVF 0xda0 > > #define CSR_SSTATUS 0x100 > #define CSR_SIE 0x104 > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > index 8cbe6e5f9c39..3e44d2fb8bf8 100644 > --- a/drivers/perf/riscv_pmu_sbi.c > +++ b/drivers/perf/riscv_pmu_sbi.c > @@ -27,7 +27,7 @@ > > #define ALT_SBI_PMU_OVERFLOW(__ovl) \ > asm volatile(ALTERNATIVE_2( \ > - "csrr %0, " __stringify(CSR_SSCOUNTOVF), \ > + "csrr %0, " __stringify(CSR_SCOUNTOVF), \ > "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ > THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \ > CONFIG_ERRATA_THEAD_PMU, \ > -- > 2.34.1 > Reviewed-by: Andrew Jones