From: Manali Shukla <manali.shukla@amd.com>
To: <kvm@vger.kernel.org>, <linux-kselftest@vger.kernel.org>
Cc: <pbonzini@redhat.com>, <seanjc@google.com>, <shuah@kernel.org>,
<nikunj@amd.com>, <thomas.lendacky@amd.com>,
<vkuznets@redhat.com>, <manali.shukla@amd.com>, <bp@alien8.de>,
<babu.moger@amd.com>, <neeraj.upadhyay@amd.com>
Subject: [PATCH v6 1/3] x86/cpufeatures: Add CPUID feature bit for Idle HLT intercept
Date: Tue, 28 Jan 2025 12:48:10 +0000 [thread overview]
Message-ID: <20250128124812.7324-2-manali.shukla@amd.com> (raw)
In-Reply-To: <20250128124812.7324-1-manali.shukla@amd.com>
From: Manali Shukla <Manali.Shukla@amd.com>
The Idle HLT Intercept feature allows for the HLT instruction
execution by a vCPU to be intercepted by the hypervisor only if there
are no pending events (V_INTR and V_NMI) for the vCPU. When the vCPU
is expected to service the pending events (V_INTR and V_NMI), the Idle
HLT intercept won’t trigger. The feature allows the hypervisor to
determine if the vCPU is idle and reduces wasteful VMEXITs.
In addition to the aforementioned use case, the Idle HLT intercept
feature is also used for enlightened guests who aim to securely manage
events without the hypervisor’s awareness. If a HLT occurs while
a virtual event is pending and the hypervisor is unaware of this
pending event (as could be the case with enlightened guests), the
absence of the Idle HLT intercept feature could result in a vCPU being
suspended indefinitely.
Presence of Idle HLT intercept feature for guests is indicated via CPUID
function 0x8000000A_EDX[30].
Signed-off-by: Manali Shukla <Manali.Shukla@amd.com>
Acked-by: Borislav Petkov (AMD) <bp@alien8.de>
---
arch/x86/include/asm/cpufeatures.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 645aa360628d..4fef0533f764 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -386,6 +386,7 @@
#define X86_FEATURE_V_SPEC_CTRL (15*32+20) /* "v_spec_ctrl" Virtual SPEC_CTRL */
#define X86_FEATURE_VNMI (15*32+25) /* "vnmi" Virtual NMI */
#define X86_FEATURE_SVME_ADDR_CHK (15*32+28) /* SVME addr check */
+#define X86_FEATURE_IDLE_HLT (15*32+30) /* IDLE HLT intercept */
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
#define X86_FEATURE_AVX512VBMI (16*32+ 1) /* "avx512vbmi" AVX512 Vector Bit Manipulation instructions*/
base-commit: eb723766b1030a23c38adf2348b7c3d1409d11f0
prerequisite-patch-id: cb345fc0d814a351df2b5788b76eee0eef9de549
prerequisite-patch-id: 71806f400cffe09f47d6231cb072cbdbd540de1b
prerequisite-patch-id: 9ea0412aab7ecd8555fcee3e9609dbfe8456d47b
prerequisite-patch-id: 3504df50cdd33958456f2e56139d76867273525c
prerequisite-patch-id: 674e56729a56cc487cb85be1a64ef561eb7bac8a
prerequisite-patch-id: 48e87354f9d6e6bd121ca32ab73cd0d7f1dce74f
prerequisite-patch-id: b32c21df6522a7396baa41d62bcad9479041d97a
prerequisite-patch-id: 0ff4b504e982db7c1dfa8ec6ac485c92a89f4af8
prerequisite-patch-id: 509018dc2fc1657debc641544e86f5a92d04bc1a
--
2.34.1
next prev parent reply other threads:[~2025-01-28 12:48 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-28 12:48 [PATCH v6 0/3] Add support for the Idle HLT intercept feature Manali Shukla
2025-01-28 12:48 ` Manali Shukla [this message]
2025-01-28 12:48 ` [PATCH v6 2/3] KVM: SVM: Add Idle HLT intercept support Manali Shukla
2025-02-25 22:07 ` Sean Christopherson
2025-02-27 8:21 ` Manali Shukla
2025-02-27 14:32 ` Sean Christopherson
2025-02-27 16:05 ` Manali Shukla
2025-02-27 16:11 ` Sean Christopherson
2025-02-28 14:58 ` Manali Shukla
2025-01-28 12:48 ` [PATCH v6 3/3] KVM: selftests: Add self IPI HLT test Manali Shukla
2025-01-29 5:26 ` Neeraj Upadhyay
2025-02-26 0:38 ` Sean Christopherson
2025-02-28 15:05 ` Manali Shukla
2025-02-10 5:06 ` [PATCH v6 0/3] Add support for the Idle HLT intercept feature Manali Shukla
2025-02-17 4:43 ` Manali Shukla
2025-02-28 17:06 ` Sean Christopherson
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