From: Andrew Jones <ajones@ventanamicro.com>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Shuah Khan <shuah@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org,
Samuel Holland <samuel.holland@sifive.com>
Subject: Re: [PATCH v3 14/17] RISC-V: KVM: add SBI extension init()/deinit() functions
Date: Thu, 13 Mar 2025 15:27:17 +0100 [thread overview]
Message-ID: <20250313-f08cee46c912f729d1829d37@orel> (raw)
In-Reply-To: <20250310151229.2365992-15-cleger@rivosinc.com>
On Mon, Mar 10, 2025 at 04:12:21PM +0100, Clément Léger wrote:
> The FWFT SBI extension will need to dynamically allocate memory and do
> init time specific initialization. Add an init/deinit callbacks that
> allows to do so.
>
> Signed-off-by: Clément Léger <cleger@rivosinc.com>
> ---
> arch/riscv/include/asm/kvm_vcpu_sbi.h | 9 +++++++++
> arch/riscv/kvm/vcpu.c | 2 ++
> arch/riscv/kvm/vcpu_sbi.c | 29 +++++++++++++++++++++++++++
> 3 files changed, 40 insertions(+)
>
> diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm/kvm_vcpu_sbi.h
> index 4ed6203cdd30..bcb90757b149 100644
> --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h
> +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h
> @@ -49,6 +49,14 @@ struct kvm_vcpu_sbi_extension {
>
> /* Extension specific probe function */
> unsigned long (*probe)(struct kvm_vcpu *vcpu);
> +
> + /*
> + * Init/deinit function called once during VCPU init/destroy. These
> + * might be use if the SBI extensions need to allocate or do specific
> + * init time only configuration.
> + */
> + int (*init)(struct kvm_vcpu *vcpu);
> + void (*deinit)(struct kvm_vcpu *vcpu);
> };
>
> void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, struct kvm_run *run);
> @@ -69,6 +77,7 @@ const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext(
> bool riscv_vcpu_supports_sbi_ext(struct kvm_vcpu *vcpu, int idx);
> int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run);
> void kvm_riscv_vcpu_sbi_init(struct kvm_vcpu *vcpu);
> +void kvm_riscv_vcpu_sbi_deinit(struct kvm_vcpu *vcpu);
>
> int kvm_riscv_vcpu_get_reg_sbi_sta(struct kvm_vcpu *vcpu, unsigned long reg_num,
> unsigned long *reg_val);
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 60d684c76c58..877bcc85c067 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -185,6 +185,8 @@ void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
>
> void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
> {
> + kvm_riscv_vcpu_sbi_deinit(vcpu);
> +
> /* Cleanup VCPU AIA context */
> kvm_riscv_vcpu_aia_deinit(vcpu);
>
> diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c
> index d1c83a77735e..858ddefd7e7f 100644
> --- a/arch/riscv/kvm/vcpu_sbi.c
> +++ b/arch/riscv/kvm/vcpu_sbi.c
> @@ -505,8 +505,37 @@ void kvm_riscv_vcpu_sbi_init(struct kvm_vcpu *vcpu)
> continue;
> }
>
> + if (!ext->default_disabled && ext->init &&
> + ext->init(vcpu) != 0) {
> + scontext->ext_status[idx] = KVM_RISCV_SBI_EXT_STATUS_UNAVAILABLE;
> + continue;
> + }
I think this new block should be below the assignment below (and it can
drop the continue) and it shouldn't check default_disabled (as I've done
below). IOW, we should always run ext->init when there is one to run here.
Otherwise, I how will it get run later?
> +
> scontext->ext_status[idx] = ext->default_disabled ?
> KVM_RISCV_SBI_EXT_STATUS_DISABLED :
> KVM_RISCV_SBI_EXT_STATUS_ENABLED;
if (ext->init && ext->init(vcpu))
scontext->ext_status[idx] = KVM_RISCV_SBI_EXT_STATUS_UNAVAILABLE;
> }
> }
> +
> +void kvm_riscv_vcpu_sbi_deinit(struct kvm_vcpu *vcpu)
> +{
> + struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context;
> + const struct kvm_riscv_sbi_extension_entry *entry;
> + const struct kvm_vcpu_sbi_extension *ext;
> + int idx, i;
> +
> + for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) {
> + entry = &sbi_ext[i];
> + ext = entry->ext_ptr;
> + idx = entry->ext_idx;
> +
> + if (idx < 0 || idx >= ARRAY_SIZE(scontext->ext_status))
> + continue;
> +
> + if (scontext->ext_status[idx] == KVM_RISCV_SBI_EXT_STATUS_UNAVAILABLE ||
> + !ext->deinit)
> + continue;
> +
> + ext->deinit(vcpu);
> + }
> +}
> --
> 2.47.2
>
Thanks,
drew
next prev parent reply other threads:[~2025-03-13 14:27 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-10 15:12 [PATCH v3 00/17] riscv: add SBI FWFT misaligned exception delegation support Clément Léger
2025-03-10 15:12 ` [PATCH v3 01/17] riscv: add Firmware Feature (FWFT) SBI extensions definitions Clément Léger
2025-03-13 12:24 ` Andrew Jones
2025-03-10 15:12 ` [PATCH v3 02/17] riscv: sbi: add FWFT extension interface Clément Léger
2025-03-13 12:39 ` Andrew Jones
2025-03-14 11:33 ` Clément Léger
2025-03-14 12:02 ` Andrew Jones
2025-03-14 12:23 ` Clément Léger
2025-03-10 15:12 ` [PATCH v3 03/17] riscv: sbi: add SBI FWFT extension calls Clément Léger
2025-03-13 12:44 ` Andrew Jones
2025-03-14 11:21 ` Clément Léger
2025-03-10 15:12 ` [PATCH v3 04/17] riscv: misaligned: request misaligned exception from SBI Clément Léger
2025-03-13 12:52 ` Andrew Jones
2025-03-10 15:12 ` [PATCH v3 05/17] riscv: misaligned: use on_each_cpu() for scalar misaligned access probing Clément Léger
2025-03-13 12:57 ` Andrew Jones
2025-03-14 11:44 ` Clément Léger
2025-03-10 15:12 ` [PATCH v3 06/17] riscv: misaligned: use correct CONFIG_ ifdef for misaligned_access_speed Clément Léger
2025-03-13 13:06 ` Andrew Jones
2025-03-14 11:47 ` Clément Léger
2025-03-10 15:12 ` [PATCH v3 07/17] riscv: misaligned: move emulated access uniformity check in a function Clément Léger
2025-03-13 13:07 ` Andrew Jones
2025-03-10 15:12 ` [PATCH v3 08/17] riscv: misaligned: add a function to check misalign trap delegability Clément Léger
2025-03-13 13:19 ` Andrew Jones
2025-03-14 11:49 ` Clément Léger
2025-03-10 15:12 ` [PATCH v3 09/17] riscv: misaligned: factorize trap handling Clément Léger
2025-03-10 15:12 ` [PATCH v3 10/17] riscv: misaligned: enable IRQs while handling misaligned accesses Clément Léger
2025-03-10 15:12 ` [PATCH v3 11/17] riscv: misaligned: use get_user() instead of __get_user() Clément Léger
2025-03-10 15:12 ` [PATCH v3 12/17] Documentation/sysctl: add riscv to unaligned-trap supported archs Clément Léger
2025-03-10 15:12 ` [PATCH v3 13/17] selftests: riscv: add misaligned access testing Clément Léger
2025-03-10 15:12 ` [PATCH v3 14/17] RISC-V: KVM: add SBI extension init()/deinit() functions Clément Léger
2025-03-13 14:27 ` Andrew Jones [this message]
2025-03-14 13:53 ` Clément Léger
2025-03-10 15:12 ` [PATCH v3 15/17] RISC-V: KVM: add SBI extension reset callback Clément Léger
2025-03-13 14:29 ` Andrew Jones
2025-03-10 15:12 ` [PATCH v3 16/17] RISC-V: KVM: add support for FWFT SBI extension Clément Léger
2025-03-13 15:18 ` Andrew Jones
2025-03-10 15:12 ` [PATCH v3 17/17] RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG Clément Léger
2025-03-13 15:23 ` Andrew Jones
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