From: Andrew Jones <ajones@ventanamicro.com>
To: Atish Patra <atish.patra@linux.dev>
Cc: Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Shuah Khan <shuah@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alexandre Ghiti <alex@ghiti.fr>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/3] KVM: riscv: selftests: Add vector extension tests
Date: Tue, 29 Apr 2025 11:15:18 +0200 [thread overview]
Message-ID: <20250429-251342442ffe2d05e6b676e1@orel> (raw)
In-Reply-To: <30b2d279-8459-4a72-aad4-29c1ece622b8@linux.dev>
On Mon, Apr 28, 2025 at 05:32:09PM -0700, Atish Patra wrote:
>
> On 4/25/25 7:20 AM, Andrew Jones wrote:
> > On Mon, Mar 24, 2025 at 05:40:31PM -0700, Atish Patra wrote:
> > > Add vector related tests with the ISA extension standard template.
> > > However, the vector registers are bit tricky as the register length is
> > > variable based on vlenb value of the system. That's why the macros are
> > > defined with a default and overidden with actual value at runtime.
> > >
> > > Signed-off-by: Atish Patra <atishp@rivosinc.com>
> > > ---
> > > tools/testing/selftests/kvm/riscv/get-reg-list.c | 111 ++++++++++++++++++++++-
> > > 1 file changed, 110 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> > > index 8515921dfdbf..576ab8eb7368 100644
> > > --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> > > +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> > > @@ -145,7 +145,9 @@ void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c)
> > > {
> > > unsigned long isa_ext_state[KVM_RISCV_ISA_EXT_MAX] = { 0 };
> > > struct vcpu_reg_sublist *s;
> > > - uint64_t feature;
> > > + uint64_t feature = 0;
> > > + u64 reg, size;
> > > + unsigned long vlenb_reg;
> > > int rc;
> > > for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++)
> > > @@ -173,6 +175,23 @@ void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c)
> > > switch (s->feature_type) {
> > > case VCPU_FEATURE_ISA_EXT:
> > > feature = RISCV_ISA_EXT_REG(s->feature);
> > > + if (s->feature == KVM_RISCV_ISA_EXT_V) {
> > > + /* Enable V extension so that we can get the vlenb register */
> > > + __vcpu_set_reg(vcpu, feature, 1);
> > We probably want to bail here if __vcpu_set_reg returns an error.
> >
> Sure. What do you mean by bail here ?
> Continue to the next reg or just assert if it returns error.
Continue to the next sublist, but now that I think of it, let's keep
this line as it is and either add a
__TEST_REQUIRE(__vcpu_has_ext(vcpu, feature),
"%s not available, skipping tests", s->name);
continue;
after it. Or, add a label to the __TEST_REQUIRE already at the bottom of
the loop and then goto that.
Thanks,
drew
prev parent reply other threads:[~2025-04-29 9:15 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-25 0:40 [PATCH 0/3] RISC-V KVM selftests improvements Atish Patra
2025-03-25 0:40 ` [PATCH 1/3] KVM: riscv: selftests: Add stval to exception handling Atish Patra
2025-04-25 12:09 ` Anup Patel
2025-04-25 13:50 ` Andrew Jones
2025-04-28 22:47 ` Atish Patra
2025-04-29 9:05 ` Andrew Jones
2025-03-25 0:40 ` [PATCH 2/3] KVM: riscv: selftests: Decode stval to identify exact exception type Atish Patra
2025-04-25 12:12 ` Anup Patel
2025-04-25 13:33 ` Andrew Jones
2025-04-28 22:48 ` Atish Patra
2025-03-25 0:40 ` [PATCH 3/3] KVM: riscv: selftests: Add vector extension tests Atish Patra
2025-04-25 12:16 ` Anup Patel
2025-04-25 14:20 ` Andrew Jones
2025-04-29 0:32 ` Atish Patra
2025-04-29 9:15 ` Andrew Jones [this message]
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