From: kernel test robot <lkp@intel.com>
To: Colton Lewis <coltonlewis@google.com>, kvm@vger.kernel.org
Cc: oe-kbuild-all@lists.linux.dev,
Paolo Bonzini <pbonzini@redhat.com>,
Jonathan Corbet <corbet@lwn.net>,
Russell King <linux@armlinux.org.uk>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Mark Rutland <mark.rutland@arm.com>,
Shuah Khan <skhan@linuxfoundation.org>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-perf-users@vger.kernel.org,
linux-kselftest@vger.kernel.org,
Colton Lewis <coltonlewis@google.com>
Subject: Re: [PATCH v2 05/23] KVM: arm64: Cleanup PMU includes
Date: Sat, 21 Jun 2025 22:56:09 +0800 [thread overview]
Message-ID: <202506212205.NmAR3sAH-lkp@intel.com> (raw)
In-Reply-To: <20250620221326.1261128-6-coltonlewis@google.com>
Hi Colton,
kernel test robot noticed the following build errors:
[auto build test ERROR on 79150772457f4d45e38b842d786240c36bb1f97f]
url: https://github.com/intel-lab-lkp/linux/commits/Colton-Lewis/arm64-cpufeature-Add-cpucap-for-HPMN0/20250621-102220
base: 79150772457f4d45e38b842d786240c36bb1f97f
patch link: https://lore.kernel.org/r/20250620221326.1261128-6-coltonlewis%40google.com
patch subject: [PATCH v2 05/23] KVM: arm64: Cleanup PMU includes
config: arm64-randconfig-004-20250621 (https://download.01.org/0day-ci/archive/20250621/202506212205.NmAR3sAH-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 10.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250621/202506212205.NmAR3sAH-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202506212205.NmAR3sAH-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/perf/arm_pmuv3.c:143:41: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD'
143 | [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/perf/arm_pmuv3.h:123:45: warning: initialized field overwritten [-Woverride-init]
123 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR 0x0041
| ^~~~~~
drivers/perf/arm_pmuv3.c:144:44: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR'
144 | [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/perf/arm_pmuv3.h:123:45: note: (near initialization for 'armv8_vulcan_perf_cache_map[0][1][0]')
123 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR 0x0041
| ^~~~~~
drivers/perf/arm_pmuv3.c:144:44: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR'
144 | [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/perf/arm_pmuv3.h:125:51: warning: initialized field overwritten [-Woverride-init]
125 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR 0x0043
| ^~~~~~
drivers/perf/arm_pmuv3.c:145:42: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR'
145 | [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/perf/arm_pmuv3.h:125:51: note: (near initialization for 'armv8_vulcan_perf_cache_map[0][1][1]')
125 | #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR 0x0043
| ^~~~~~
drivers/perf/arm_pmuv3.c:145:42: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR'
145 | [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/perf/arm_pmuv3.h:134:44: warning: initialized field overwritten [-Woverride-init]
134 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD 0x004E
| ^~~~~~
drivers/perf/arm_pmuv3.c:147:44: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD'
147 | [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/perf/arm_pmuv3.h:134:44: note: (near initialization for 'armv8_vulcan_perf_cache_map[3][0][0]')
134 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD 0x004E
| ^~~~~~
drivers/perf/arm_pmuv3.c:147:44: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD'
147 | [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/perf/arm_pmuv3.h:135:44: warning: initialized field overwritten [-Woverride-init]
135 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR 0x004F
| ^~~~~~
drivers/perf/arm_pmuv3.c:148:45: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR'
148 | [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/perf/arm_pmuv3.h:135:44: note: (near initialization for 'armv8_vulcan_perf_cache_map[3][1][0]')
135 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR 0x004F
| ^~~~~~
drivers/perf/arm_pmuv3.c:148:45: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR'
148 | [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/perf/arm_pmuv3.h:132:50: warning: initialized field overwritten [-Woverride-init]
132 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD 0x004C
| ^~~~~~
drivers/perf/arm_pmuv3.c:149:42: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD'
149 | [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/perf/arm_pmuv3.h:132:50: note: (near initialization for 'armv8_vulcan_perf_cache_map[3][0][1]')
132 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD 0x004C
| ^~~~~~
drivers/perf/arm_pmuv3.c:149:42: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD'
149 | [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/perf/arm_pmuv3.h:133:50: warning: initialized field overwritten [-Woverride-init]
133 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR 0x004D
| ^~~~~~
drivers/perf/arm_pmuv3.c:150:43: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR'
150 | [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/perf/arm_pmuv3.h:133:50: note: (near initialization for 'armv8_vulcan_perf_cache_map[3][1][1]')
133 | #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR 0x004D
| ^~~~~~
drivers/perf/arm_pmuv3.c:150:43: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR'
150 | [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/perf/arm_pmuv3.h:149:46: warning: initialized field overwritten [-Woverride-init]
149 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD 0x0060
| ^~~~~~
drivers/perf/arm_pmuv3.c:152:44: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD'
152 | [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/perf/arm_pmuv3.h:149:46: note: (near initialization for 'armv8_vulcan_perf_cache_map[6][0][0]')
149 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD 0x0060
| ^~~~~~
drivers/perf/arm_pmuv3.c:152:44: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD'
152 | [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/perf/arm_pmuv3.h:150:46: warning: initialized field overwritten [-Woverride-init]
150 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR 0x0061
| ^~~~~~
drivers/perf/arm_pmuv3.c:153:45: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR'
153 | [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/perf/arm_pmuv3.h:150:46: note: (near initialization for 'armv8_vulcan_perf_cache_map[6][1][0]')
150 | #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR 0x0061
| ^~~~~~
drivers/perf/arm_pmuv3.c:153:45: note: in expansion of macro 'ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR'
153 | [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/perf/arm_pmuv3.c: In function 'armv8pmu_enable_event_counter':
>> drivers/perf/arm_pmuv3.c:680:2: error: implicit declaration of function 'kvm_set_pmu_events' [-Werror=implicit-function-declaration]
680 | kvm_set_pmu_events(mask, attr);
| ^~~~~~~~~~~~~~~~~~
drivers/perf/arm_pmuv3.c: In function 'armv8pmu_disable_event_counter':
>> drivers/perf/arm_pmuv3.c:702:2: error: implicit declaration of function 'kvm_clr_pmu_events' [-Werror=implicit-function-declaration]
702 | kvm_clr_pmu_events(mask);
| ^~~~~~~~~~~~~~~~~~
drivers/perf/arm_pmuv3.c: In function 'update_pmuserenr':
>> drivers/perf/arm_pmuv3.c:757:6: error: implicit declaration of function 'kvm_set_pmuserenr' [-Werror=implicit-function-declaration]
757 | if (kvm_set_pmuserenr(val))
| ^~~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
vim +/kvm_set_pmu_events +680 drivers/perf/arm_pmuv3.c
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 674
9343c790e6de7e drivers/perf/arm_pmuv3.c James Clark 2023-12-11 675 static void armv8pmu_enable_event_counter(struct perf_event *event)
c13207905340d8 arch/arm64/kernel/perf_event.c Suzuki K Poulose 2018-07-10 676 {
d1947bc4bc63e5 arch/arm64/kernel/perf_event.c Andrew Murray 2019-04-09 677 struct perf_event_attr *attr = &event->attr;
a4a6e2078d85a9 drivers/perf/arm_pmuv3.c Rob Herring (Arm 2024-07-31 678) u64 mask = armv8pmu_event_cnten_mask(event);
d1947bc4bc63e5 arch/arm64/kernel/perf_event.c Andrew Murray 2019-04-09 679
29227d6ea1572b arch/arm64/kernel/perf_event.c Robin Murphy 2020-03-17 @680 kvm_set_pmu_events(mask, attr);
d1947bc4bc63e5 arch/arm64/kernel/perf_event.c Andrew Murray 2019-04-09 681
d1947bc4bc63e5 arch/arm64/kernel/perf_event.c Andrew Murray 2019-04-09 682 /* We rely on the hypervisor switch code to enable guest counters */
29227d6ea1572b arch/arm64/kernel/perf_event.c Robin Murphy 2020-03-17 683 if (!kvm_pmu_counter_deferred(attr))
29227d6ea1572b arch/arm64/kernel/perf_event.c Robin Murphy 2020-03-17 684 armv8pmu_enable_counter(mask);
c13207905340d8 arch/arm64/kernel/perf_event.c Suzuki K Poulose 2018-07-10 685 }
c13207905340d8 arch/arm64/kernel/perf_event.c Suzuki K Poulose 2018-07-10 686
a4a6e2078d85a9 drivers/perf/arm_pmuv3.c Rob Herring (Arm 2024-07-31 687) static void armv8pmu_disable_counter(u64 mask)
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 688 {
df29ddf4f04b00 drivers/perf/arm_pmuv3.c Marc Zyngier 2023-03-17 689 write_pmcntenclr(mask);
0fdf1bb75953a6 arch/arm64/kernel/perf_event.c Mark Rutland 2020-09-24 690 /*
0fdf1bb75953a6 arch/arm64/kernel/perf_event.c Mark Rutland 2020-09-24 691 * Make sure the effects of disabling the counter are visible before we
0fdf1bb75953a6 arch/arm64/kernel/perf_event.c Mark Rutland 2020-09-24 692 * start configuring the event.
0fdf1bb75953a6 arch/arm64/kernel/perf_event.c Mark Rutland 2020-09-24 693 */
0fdf1bb75953a6 arch/arm64/kernel/perf_event.c Mark Rutland 2020-09-24 694 isb();
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 695 }
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 696
9343c790e6de7e drivers/perf/arm_pmuv3.c James Clark 2023-12-11 697 static void armv8pmu_disable_event_counter(struct perf_event *event)
c13207905340d8 arch/arm64/kernel/perf_event.c Suzuki K Poulose 2018-07-10 698 {
d1947bc4bc63e5 arch/arm64/kernel/perf_event.c Andrew Murray 2019-04-09 699 struct perf_event_attr *attr = &event->attr;
a4a6e2078d85a9 drivers/perf/arm_pmuv3.c Rob Herring (Arm 2024-07-31 700) u64 mask = armv8pmu_event_cnten_mask(event);
d1947bc4bc63e5 arch/arm64/kernel/perf_event.c Andrew Murray 2019-04-09 701
29227d6ea1572b arch/arm64/kernel/perf_event.c Robin Murphy 2020-03-17 @702 kvm_clr_pmu_events(mask);
d1947bc4bc63e5 arch/arm64/kernel/perf_event.c Andrew Murray 2019-04-09 703
d1947bc4bc63e5 arch/arm64/kernel/perf_event.c Andrew Murray 2019-04-09 704 /* We rely on the hypervisor switch code to disable guest counters */
29227d6ea1572b arch/arm64/kernel/perf_event.c Robin Murphy 2020-03-17 705 if (!kvm_pmu_counter_deferred(attr))
29227d6ea1572b arch/arm64/kernel/perf_event.c Robin Murphy 2020-03-17 706 armv8pmu_disable_counter(mask);
d1947bc4bc63e5 arch/arm64/kernel/perf_event.c Andrew Murray 2019-04-09 707 }
c13207905340d8 arch/arm64/kernel/perf_event.c Suzuki K Poulose 2018-07-10 708
a4a6e2078d85a9 drivers/perf/arm_pmuv3.c Rob Herring (Arm 2024-07-31 709) static void armv8pmu_enable_intens(u64 mask)
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 710 {
df29ddf4f04b00 drivers/perf/arm_pmuv3.c Marc Zyngier 2023-03-17 711 write_pmintenset(mask);
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 712 }
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 713
9343c790e6de7e drivers/perf/arm_pmuv3.c James Clark 2023-12-11 714 static void armv8pmu_enable_event_irq(struct perf_event *event)
c13207905340d8 arch/arm64/kernel/perf_event.c Suzuki K Poulose 2018-07-10 715 {
bf5ffc8c80e0cf drivers/perf/arm_pmuv3.c Rob Herring (Arm 2024-07-31 716) armv8pmu_enable_intens(BIT(event->hw.idx));
c13207905340d8 arch/arm64/kernel/perf_event.c Suzuki K Poulose 2018-07-10 717 }
c13207905340d8 arch/arm64/kernel/perf_event.c Suzuki K Poulose 2018-07-10 718
a4a6e2078d85a9 drivers/perf/arm_pmuv3.c Rob Herring (Arm 2024-07-31 719) static void armv8pmu_disable_intens(u64 mask)
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 720 {
df29ddf4f04b00 drivers/perf/arm_pmuv3.c Marc Zyngier 2023-03-17 721 write_pmintenclr(mask);
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 722 isb();
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 723 /* Clear the overflow flag in case an interrupt is pending. */
df29ddf4f04b00 drivers/perf/arm_pmuv3.c Marc Zyngier 2023-03-17 724 write_pmovsclr(mask);
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 725 isb();
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 726 }
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 727
9343c790e6de7e drivers/perf/arm_pmuv3.c James Clark 2023-12-11 728 static void armv8pmu_disable_event_irq(struct perf_event *event)
c13207905340d8 arch/arm64/kernel/perf_event.c Suzuki K Poulose 2018-07-10 729 {
bf5ffc8c80e0cf drivers/perf/arm_pmuv3.c Rob Herring (Arm 2024-07-31 730) armv8pmu_disable_intens(BIT(event->hw.idx));
c13207905340d8 arch/arm64/kernel/perf_event.c Suzuki K Poulose 2018-07-10 731 }
c13207905340d8 arch/arm64/kernel/perf_event.c Suzuki K Poulose 2018-07-10 732
a4a6e2078d85a9 drivers/perf/arm_pmuv3.c Rob Herring (Arm 2024-07-31 733) static u64 armv8pmu_getreset_flags(void)
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 734 {
a4a6e2078d85a9 drivers/perf/arm_pmuv3.c Rob Herring (Arm 2024-07-31 735) u64 value;
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 736
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 737 /* Read */
df29ddf4f04b00 drivers/perf/arm_pmuv3.c Marc Zyngier 2023-03-17 738 value = read_pmovsclr();
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 739
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 740 /* Write to clear flags */
d30f09b6d7de5d drivers/perf/arm_pmuv3.c James Clark 2023-12-11 741 value &= ARMV8_PMU_OVERFLOWED_MASK;
df29ddf4f04b00 drivers/perf/arm_pmuv3.c Marc Zyngier 2023-03-17 742 write_pmovsclr(value);
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 743
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 744 return value;
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 745 }
030896885ade0a arch/arm64/kernel/perf_event.c Will Deacon 2012-03-05 746
0c2f9acf6ae741 drivers/perf/arm_pmuv3.c Reiji Watanabe 2023-06-02 747 static void update_pmuserenr(u64 val)
0c2f9acf6ae741 drivers/perf/arm_pmuv3.c Reiji Watanabe 2023-06-02 748 {
0c2f9acf6ae741 drivers/perf/arm_pmuv3.c Reiji Watanabe 2023-06-02 749 lockdep_assert_irqs_disabled();
0c2f9acf6ae741 drivers/perf/arm_pmuv3.c Reiji Watanabe 2023-06-02 750
0c2f9acf6ae741 drivers/perf/arm_pmuv3.c Reiji Watanabe 2023-06-02 751 /*
0c2f9acf6ae741 drivers/perf/arm_pmuv3.c Reiji Watanabe 2023-06-02 752 * The current PMUSERENR_EL0 value might be the value for the guest.
0c2f9acf6ae741 drivers/perf/arm_pmuv3.c Reiji Watanabe 2023-06-02 753 * If that's the case, have KVM keep tracking of the register value
0c2f9acf6ae741 drivers/perf/arm_pmuv3.c Reiji Watanabe 2023-06-02 754 * for the host EL0 so that KVM can restore it before returning to
0c2f9acf6ae741 drivers/perf/arm_pmuv3.c Reiji Watanabe 2023-06-02 755 * the host EL0. Otherwise, update the register now.
0c2f9acf6ae741 drivers/perf/arm_pmuv3.c Reiji Watanabe 2023-06-02 756 */
0c2f9acf6ae741 drivers/perf/arm_pmuv3.c Reiji Watanabe 2023-06-02 @757 if (kvm_set_pmuserenr(val))
0c2f9acf6ae741 drivers/perf/arm_pmuv3.c Reiji Watanabe 2023-06-02 758 return;
0c2f9acf6ae741 drivers/perf/arm_pmuv3.c Reiji Watanabe 2023-06-02 759
0c2f9acf6ae741 drivers/perf/arm_pmuv3.c Reiji Watanabe 2023-06-02 760 write_pmuserenr(val);
0c2f9acf6ae741 drivers/perf/arm_pmuv3.c Reiji Watanabe 2023-06-02 761 }
0c2f9acf6ae741 drivers/perf/arm_pmuv3.c Reiji Watanabe 2023-06-02 762
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
next prev parent reply other threads:[~2025-06-21 14:57 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-20 22:13 [PATCH v2 00/23] ARM64 PMU Partitioning Colton Lewis
2025-06-20 22:13 ` [PATCH v2 01/23] arm64: cpufeature: Add cpucap for HPMN0 Colton Lewis
2025-06-21 0:44 ` Oliver Upton
2025-06-23 18:25 ` Colton Lewis
2025-06-24 7:28 ` Oliver Upton
2025-06-24 20:05 ` Colton Lewis
2025-06-20 22:13 ` [PATCH v2 02/23] arm64: Generate sign macro for sysreg Enums Colton Lewis
2025-06-20 22:13 ` [PATCH v2 03/23] arm64: cpufeature: Add cpucap for PMICNTR Colton Lewis
2025-06-21 0:45 ` Oliver Upton
2025-06-23 18:25 ` Colton Lewis
2025-06-20 22:13 ` [PATCH v2 04/23] arm64: Define PMI{CNTR,FILTR}_EL0 as undef_access Colton Lewis
2025-06-20 22:13 ` [PATCH v2 05/23] KVM: arm64: Cleanup PMU includes Colton Lewis
2025-06-21 14:56 ` kernel test robot [this message]
2025-06-23 22:04 ` Colton Lewis
2025-06-20 22:13 ` [PATCH v2 06/23] KVM: arm64: Reorganize PMU functions Colton Lewis
2025-06-20 22:13 ` [PATCH v2 07/23] perf: arm_pmuv3: Introduce method to partition the PMU Colton Lewis
2025-06-21 1:06 ` Oliver Upton
2025-06-23 18:26 ` Colton Lewis
2025-06-24 7:05 ` Oliver Upton
2025-06-24 20:05 ` Colton Lewis
2025-06-20 22:13 ` [PATCH v2 07/23] perf: pmuv3: " Colton Lewis
2025-06-20 22:13 ` [PATCH v2 08/23] perf: arm_pmuv3: Generalize counter bitmasks Colton Lewis
2025-06-20 22:13 ` [PATCH v2 09/23] perf: arm_pmuv3: Keep out of guest counter partition Colton Lewis
2025-06-20 22:13 ` [PATCH v2 10/23] KVM: arm64: Correct kvm_arm_pmu_get_max_counters() Colton Lewis
2025-06-20 22:13 ` [PATCH v2 11/23] KVM: arm64: Set up FGT for Partitioned PMU Colton Lewis
2025-06-20 22:13 ` [PATCH v2 12/23] KVM: arm64: Writethrough trapped PMEVTYPER register Colton Lewis
2025-06-20 22:13 ` [PATCH v2 13/23] KVM: arm64: Use physical PMSELR for PMXEVTYPER if partitioned Colton Lewis
2025-06-20 22:13 ` [PATCH v2 14/23] KVM: arm64: Writethrough trapped PMOVS register Colton Lewis
2025-06-20 22:13 ` [PATCH v2 15/23] KVM: arm64: Write fast path PMU register handlers Colton Lewis
2025-06-20 22:13 ` [PATCH v2 16/23] KVM: arm64: Setup MDCR_EL2 to handle a partitioned PMU Colton Lewis
2025-06-20 22:13 ` [PATCH v2 17/23] KVM: arm64: Account for partitioning in PMCR_EL0 access Colton Lewis
2025-06-22 9:32 ` kernel test robot
2025-06-23 22:11 ` Colton Lewis
2025-06-20 22:13 ` [PATCH v2 18/23] KVM: arm64: Context swap Partitioned PMU guest registers Colton Lewis
2025-06-20 22:13 ` [PATCH v2 19/23] KVM: arm64: Enforce PMU event filter at vcpu_load() Colton Lewis
2025-06-20 22:13 ` [PATCH v2 20/23] perf: arm_pmuv3: Handle IRQs for Partitioned PMU guest counters Colton Lewis
2025-06-20 22:13 ` [PATCH v2 20/23] perf: pmuv3: " Colton Lewis
2025-06-20 22:13 ` [PATCH v2 21/23] KVM: arm64: Inject recorded guest interrupts Colton Lewis
2025-06-20 22:13 ` [PATCH v2 22/23] KVM: arm64: Add ioctl to partition the PMU when supported Colton Lewis
2025-06-20 22:13 ` [PATCH v2 23/23] KVM: arm64: selftests: Add test case for partitioned PMU Colton Lewis
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