From: Sergey Matyukevich <geomatsi@gmail.com>
To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-kselftest@vger.kernel.org
Cc: Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alexandre Ghiti <alex@ghiti.fr>, Oleg Nesterov <oleg@redhat.com>,
Shuah Khan <shuah@kernel.org>, Thomas Huth <thuth@redhat.com>,
Charlie Jenkins <charlie@rivosinc.com>,
Andy Chiu <andybnac@gmail.com>,
Samuel Holland <samuel.holland@sifive.com>,
Joel Granados <joel.granados@kernel.org>,
Conor Dooley <conor.dooley@microchip.com>,
Yong-Xuan Wang <yongxuan.wang@sifive.com>,
Heiko Stuebner <heiko@sntech.de>, Guo Ren <guoren@kernel.org>,
Sergey Matyukevich <geomatsi@gmail.com>
Subject: [PATCH v5 2/9] riscv: vector: init vector context with proper vlenb
Date: Sun, 14 Dec 2025 19:35:06 +0300 [thread overview]
Message-ID: <20251214163537.1054292-3-geomatsi@gmail.com> (raw)
In-Reply-To: <20251214163537.1054292-1-geomatsi@gmail.com>
The vstate in thread_struct is zeroed when the vector context is
initialized. That includes read-only register vlenb, which holds
the vector register length in bytes. Zeroed state persists until
mstatus.VS becomes 'dirty' and a context switch saves the actual
hardware values.
This can expose the zero vlenb value to the user-space in early
debug scenarios, e.g. when ptrace attaches to a traced process
early, before any vector instruction except the first one was
executed.
Fix this by specifying proper vlenb on vector context init.
Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
---
arch/riscv/kernel/vector.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
index 3ed071dab9d8..b112166d51e9 100644
--- a/arch/riscv/kernel/vector.c
+++ b/arch/riscv/kernel/vector.c
@@ -111,8 +111,8 @@ bool insn_is_vector(u32 insn_buf)
return false;
}
-static int riscv_v_thread_zalloc(struct kmem_cache *cache,
- struct __riscv_v_ext_state *ctx)
+static int riscv_v_thread_ctx_alloc(struct kmem_cache *cache,
+ struct __riscv_v_ext_state *ctx)
{
void *datap;
@@ -122,13 +122,15 @@ static int riscv_v_thread_zalloc(struct kmem_cache *cache,
ctx->datap = datap;
memset(ctx, 0, offsetof(struct __riscv_v_ext_state, datap));
+ ctx->vlenb = riscv_v_vsize / 32;
+
return 0;
}
void riscv_v_thread_alloc(struct task_struct *tsk)
{
#ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE
- riscv_v_thread_zalloc(riscv_v_kernel_cachep, &tsk->thread.kernel_vstate);
+ riscv_v_thread_ctx_alloc(riscv_v_kernel_cachep, &tsk->thread.kernel_vstate);
#endif
}
@@ -214,12 +216,14 @@ bool riscv_v_first_use_handler(struct pt_regs *regs)
* context where VS has been off. So, try to allocate the user's V
* context and resume execution.
*/
- if (riscv_v_thread_zalloc(riscv_v_user_cachep, ¤t->thread.vstate)) {
+ if (riscv_v_thread_ctx_alloc(riscv_v_user_cachep, ¤t->thread.vstate)) {
force_sig(SIGBUS);
return true;
}
+
riscv_v_vstate_on(regs);
riscv_v_vstate_set_restore(current, regs);
+
return true;
}
--
2.52.0
next prev parent reply other threads:[~2025-12-14 16:35 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-14 16:35 [PATCH v5 0/9] riscv: vector: misc ptrace fixes for debug use-cases Sergey Matyukevich
2025-12-14 16:35 ` [PATCH v5 1/9] riscv: ptrace: return ENODATA for inactive vector extension Sergey Matyukevich
2026-01-07 6:48 ` Andy Chiu
2025-12-14 16:35 ` Sergey Matyukevich [this message]
2026-01-07 6:49 ` [PATCH v5 2/9] riscv: vector: init vector context with proper vlenb Andy Chiu
2026-01-19 20:48 ` Sergey Matyukevich
2025-12-14 16:35 ` [PATCH v5 3/9] riscv: csr: define vtype register elements Sergey Matyukevich
2026-01-21 21:04 ` Andy Chiu
2025-12-14 16:35 ` [PATCH v5 4/9] riscv: ptrace: validate input vector csr registers Sergey Matyukevich
2026-01-21 21:07 ` Andy Chiu
2025-12-14 16:35 ` [PATCH v5 5/9] selftests: riscv: test ptrace vector interface Sergey Matyukevich
2025-12-14 16:35 ` [PATCH v5 6/9] selftests: riscv: verify initial vector state with ptrace Sergey Matyukevich
2026-01-21 21:33 ` Andy Chiu
2025-12-14 16:35 ` [PATCH v5 7/9] selftests: riscv: verify syscalls discard vector context Sergey Matyukevich
2026-01-21 21:37 ` Andy Chiu
2025-12-14 16:35 ` [PATCH v5 8/9] selftests: riscv: verify ptrace rejects invalid vector csr inputs Sergey Matyukevich
2025-12-14 16:35 ` [PATCH v5 9/9] selftests: riscv: verify ptrace accepts valid vector csr values Sergey Matyukevich
2026-01-21 21:47 ` [PATCH v5 0/9] riscv: vector: misc ptrace fixes for debug use-cases Andy Chiu
2026-01-24 8:30 ` patchwork-bot+linux-riscv
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