[PATCH v5 3/9] riscv: csr: define vtype register elements

Sergey Matyukevich
2025-12-14T16:35:51Z

Define masks and shifts for vtype CSR according to the vector specs:
- v0.7.1 used in early T-Head cores, known as xtheadvector in the kernel
- v1.0

Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
---
arch/riscv/include/asm/csr.h | 17 +++++++++++++++++
1 file changed, 17 insertions(+)

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 4a37a98398ad..38f16538b35c 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -444,6 +444,23 @@
#define CSR_VTYPE 0xc21
#define CSR_VLENB 0xc22

+#define VTYPE_VLMUL _AC(7, UL)
+#define VTYPE_VLMUL_FRAC _AC(4, UL)
+#define VTYPE_VSEW_SHIFT 3
+#define VTYPE_VSEW (_AC(7, UL) << VTYPE_VSEW_SHIFT)
+#define VTYPE_VTA_SHIFT 6
+#define VTYPE_VTA (_AC(1, UL) << VTYPE_VTA_SHIFT)
+#define VTYPE_VMA_SHIFT 7
+#define VTYPE_VMA (_AC(1, UL) << VTYPE_VMA_SHIFT)
+#define VTYPE_VILL_SHIFT (__riscv_xlen - 1)
+#define VTYPE_VILL (_AC(1, UL) << VTYPE_VILL_SHIFT)
+
+#define VTYPE_VLMUL_THEAD _AC(3, UL)
+#define VTYPE_VSEW_THEAD_SHIFT 2
+#define VTYPE_VSEW_THEAD (_AC(7, UL) << VTYPE_VSEW_THEAD_SHIFT)
+#define VTYPE_VEDIV_THEAD_SHIFT 5
+#define VTYPE_VEDIV_THEAD (_AC(3, UL) << VTYPE_VEDIV_THEAD_SHIFT)
+
/* Scalar Crypto Extension - Entropy */
#define CSR_SEED 0x015
#define SEED_OPST_MASK _AC(0xC0000000, UL)
--
2.52.0