From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-oo1-f74.google.com (mail-oo1-f74.google.com [209.85.161.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C19D3195F6 for ; Mon, 9 Feb 2026 22:40:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.161.74 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770676853; cv=none; b=J7eujhZmvN28gaaal8KjcvFcck9+s+3IKsf7ZVe7dYUEgYWA3cwmQ7XzcH9QH1uEOXL7e14Aa9zs0RouGIspwLh965HXhwA2GDA41MyEaNXJueVTsxP1TWRpygBtffiFV4AuQVpF1nD1qGjZpxPWGtYGS/VoV5sI6P1BChtRdCY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770676853; c=relaxed/simple; bh=dXTvn4qocYHpwQDXijQpcg4yhTZjehQMfz5QbgqWF8w=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=IIn7pJdzLWbuva4fer99qktcQPdO9jKV4+YLilINm9SwGpOJqSZd7yRpTyjNIa+75E3f8aG1n7WlTsJawm8DYje7Ok4vMNcx3ji/ofow/Z+T1DJPedCN4e2grTpz0SUmv4KGcKEfTcObShHBpAk4B8AGGSR04Yzx53d5Q+xMSCc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--coltonlewis.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=VXRB4Z5B; arc=none smtp.client-ip=209.85.161.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--coltonlewis.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="VXRB4Z5B" Received: by mail-oo1-f74.google.com with SMTP id 006d021491bc7-66b8c7f0debso1310337eaf.3 for ; Mon, 09 Feb 2026 14:40:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1770676849; x=1771281649; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=imeQaLzXrnVqs2xwe1B4fumETENHcf/y9Tb2xZBjKCc=; b=VXRB4Z5BPWZUplDuhiKWgqT0op4G6BioUYx53Cw8Y+8LUxjNK4sb9M1TdUvC0mynvZ Q+K54u2Wa675nkRHkzh+z834mzpB3sU3zQ+yG3DDe7xEJD+HL0SCI7CmHjLm02TexLhZ 2bxAF09MlXkbiGQ4U6eVMyCUuGP6++9Kw0jGFHyLkSxzGZ2I1pdRExF37MZNkD0VErHN VGrZB9P/tczRtyLwsVYGhWjqtPGtjEmz9ZWGabehT/FSifXdJNUH/F8YQvyVliumawk4 9Zfp6Z9mjXhnZj/azjxm6ROeJrobsIRCcfHsa7TaY3gfGrvDNaz7L6RYyt77GODfNgaQ cf+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770676849; x=1771281649; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=imeQaLzXrnVqs2xwe1B4fumETENHcf/y9Tb2xZBjKCc=; b=N5CyseewclGtenAinyqFo9x/E47/V/dHHp83jwoAZhYjKTk6KamEZYJGmaANwwKCuF m0sHDywRLqgPtPZcVmvKjxt13JcnASzfD1ft4MoqgGowj8B3dRSNCmOeZNutTBf+HyKs bD1hQKSLMw0AnB8UdAipqIF/GGDckSyL9JFBn9JvsXfh+YrbV6u9/dVlA5Z7alrUvWEL kFrgiZTjA5XZyBgTm+/EKuO4HsIOOLizgtnDdlgU4+PVRycxOusQv+LaBvXa3d0Ktc1o oX//YiSR2w9Eia1IEgYqF0EqTr4W8YnNNjJAbiVHsM69/b+qbi0vaPvoO6N4QrcA4FsR wkjg== X-Forwarded-Encrypted: i=1; AJvYcCVhAYWumKegMyhStBT6OnyK9pZXs2G8k6hDC2V5v1HgQsiA+zttEDY6u30jRs/0UQajXpUniOub3aTrBIDLPnQ=@vger.kernel.org X-Gm-Message-State: AOJu0YyoLvNGLQIOvnVotiiJe9Cm1KGzgD4JtzNPc78hcNjRrTh5cJR4 Vg95drqm1n+gGXBaQMlrGPiV1j0iQCvIcHNMWhZ4gP55f7o3gToI6FHWU6b03qzaJi2PeQ66D17 no/4GXOqgg/yrqfYV17rcsHeoQw== X-Received: from jabfq6.prod.google.com ([2002:a05:6638:6506:b0:5ce:3e9c:22c9]) (user=coltonlewis job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6820:3088:b0:662:f61e:759d with SMTP id 006d021491bc7-66d0c666b89mr6055036eaf.62.1770676849224; Mon, 09 Feb 2026 14:40:49 -0800 (PST) Date: Mon, 9 Feb 2026 22:14:00 +0000 In-Reply-To: <20260209221414.2169465-1-coltonlewis@google.com> Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260209221414.2169465-1-coltonlewis@google.com> X-Mailer: git-send-email 2.53.0.rc2.204.g2597b5adb4-goog Message-ID: <20260209221414.2169465-6-coltonlewis@google.com> Subject: [PATCH v6 05/19] perf: arm_pmuv3: Generalize counter bitmasks From: Colton Lewis To: kvm@vger.kernel.org Cc: Alexandru Elisei , Paolo Bonzini , Jonathan Corbet , Russell King , Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Mingwei Zhang , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Mark Rutland , Shuah Khan , Ganapatrao Kulkarni , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org, Colton Lewis Content-Type: text/plain; charset="UTF-8" The OVSR bitmasks are valid for enable and interrupt registers as well as overflow registers. Generalize the names. Acked-by: Mark Rutland Signed-off-by: Colton Lewis --- drivers/perf/arm_pmuv3.c | 4 ++-- include/linux/perf/arm_pmuv3.h | 14 +++++++------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index 798c93678e97c..b37908fad3249 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -546,7 +546,7 @@ static u64 armv8pmu_pmcr_n_read(void) static int armv8pmu_has_overflowed(u64 pmovsr) { - return !!(pmovsr & ARMV8_PMU_OVERFLOWED_MASK); + return !!(pmovsr & ARMV8_PMU_CNT_MASK_ALL); } static int armv8pmu_counter_has_overflowed(u64 pmnc, int idx) @@ -782,7 +782,7 @@ static u64 armv8pmu_getreset_flags(void) value = read_pmovsclr(); /* Write to clear flags */ - value &= ARMV8_PMU_OVERFLOWED_MASK; + value &= ARMV8_PMU_CNT_MASK_ALL; write_pmovsclr(value); return value; diff --git a/include/linux/perf/arm_pmuv3.h b/include/linux/perf/arm_pmuv3.h index d698efba28a27..fd2a34b4a64d1 100644 --- a/include/linux/perf/arm_pmuv3.h +++ b/include/linux/perf/arm_pmuv3.h @@ -224,14 +224,14 @@ ARMV8_PMU_PMCR_LC | ARMV8_PMU_PMCR_LP) /* - * PMOVSR: counters overflow flag status reg + * Counter bitmask layouts for overflow, enable, and interrupts */ -#define ARMV8_PMU_OVSR_P GENMASK(30, 0) -#define ARMV8_PMU_OVSR_C BIT(31) -#define ARMV8_PMU_OVSR_F BIT_ULL(32) /* arm64 only */ -/* Mask for writable bits is both P and C fields */ -#define ARMV8_PMU_OVERFLOWED_MASK (ARMV8_PMU_OVSR_P | ARMV8_PMU_OVSR_C | \ - ARMV8_PMU_OVSR_F) +#define ARMV8_PMU_CNT_MASK_P GENMASK(30, 0) +#define ARMV8_PMU_CNT_MASK_C BIT(31) +#define ARMV8_PMU_CNT_MASK_F BIT_ULL(32) /* arm64 only */ +#define ARMV8_PMU_CNT_MASK_ALL (ARMV8_PMU_CNT_MASK_P | \ + ARMV8_PMU_CNT_MASK_C | \ + ARMV8_PMU_CNT_MASK_F) /* * PMXEVTYPER: Event selection reg -- 2.53.0.rc2.204.g2597b5adb4-goog