From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-oi1-f201.google.com (mail-oi1-f201.google.com [209.85.167.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E5AF3AA1BB for ; Fri, 12 Jun 2026 19:29:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781292562; cv=none; b=ot0F0vnJQeE2sn0kNmkVhYPFdfwFQ7Ykgw16c/442pFujUGuVZhCtzdngD+SPEdM6rxIBFQix2uNVaeyps8uMyxgHMPR7jcH8VjAdUaHy+8f7P5+VIuj0KWUU91W8Sz7t/UgofbBepAYMoETYtUEu9VTsq1Epft2AJC6hiDHYFE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781292562; c=relaxed/simple; bh=lsvew6Pa1zH160wbrvXpJuTmj03ydii6m96IOxqlLDw=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=SSaFzOlMArp9cjPUe1ARYt1BS/X3aM/wLozR0uzi3fqf/3aP85VLwkqCEz2vSsbxi9QqcrZU5korqdlPlHc978RBnu8g7Nat5/cdsbW6049OVyX9K4nexFZM/sH5jrHet3fA7+ejzr/pQcMcf4CTHzsG6p3UVwFeTgnn1JugQt8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--coltonlewis.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=MQIMTSxO; arc=none smtp.client-ip=209.85.167.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--coltonlewis.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="MQIMTSxO" Received: by mail-oi1-f201.google.com with SMTP id 5614622812f47-486d0cff483so3285509b6e.2 for ; Fri, 12 Jun 2026 12:29:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1781292556; x=1781897356; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=pVFHxuaku3ZzfsFio1NduM8zq/i0jn84Pu2i1DJARd0=; b=MQIMTSxOEPAXR1b693hD51AE+fLk9BzCgNbno/XYEgZJt2gHSChCAoSUX3+jfGNzBg ohW0s7076TzVo4OgYP4Fizg/ijnQRJZdwcNie14xB3BjIbLbvkUaowkd5jtgDb7RBwDm YDOwrxC5LosPAYGA/t9SM+IyC/hoPGH6WGEbdBaOUYnR9Zch9vN/PTl6PmBWBjHTs0c8 WjEWuB3UBgr2PQCA73KbquBkMZQYG8cqOG0wkVPsSPj96ie0E/+CLbyvzYy4KFDn7Xne a9ZhC1Y34GAz0j7y9qs9p28wxgtEHfYLKmPdXN7cLfpdHCh/xnFmouLvijvdT2vjHDGB XFzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781292556; x=1781897356; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=pVFHxuaku3ZzfsFio1NduM8zq/i0jn84Pu2i1DJARd0=; b=tDv8a2Meqtdet0voADwQqp5yCLiVBUZEmG/k32K7rVL6eqq5T7unXj8G0aRQMhriGR kl2FqmMybKAPnO03iKJsIRZDFLljbEMOFDYm6G12v1rmkDtIVRelaEAnazggsjDPMf3e RMhIOX7M2YN88x8Y92oxygJ17EKq7DZzrgdkskHjWj0IVRMaBUAWxGe+X+UFUyeZeCCL V4H4uzjLvehGddDg9ag8Tb4YAdAcbmYrIQ5xnb5BB6tqCNoB2cvh0VgMORI9Krapj6ov aUDr1TC15FAwYXrHsLMiKE9rxKLFAZml69U5JbTPiwAS4Fm0Iu6JoCZb2DNpFg0qqbBL Czvg== X-Forwarded-Encrypted: i=1; AFNElJ8tsl0mi3i9q3MIzsz+XAqErFNZsDTxERV0nr1VcBPl9mPEkwMNmNujJLPEpgD3fY/jDHXaliBjaH04Jut4wls=@vger.kernel.org X-Gm-Message-State: AOJu0YxxF3GkOyhYoHKNxbBBg+bTh9KuH/NANuwFchLG3L1TEZP5IIKj zamIWQgYgEge2eEOE8FjhRqNZt9MGKuVuXyf9zH49b1JBIfqJ3AMB+9Ejxzt0tbfWYZlME/FQ9m 4qg/aecl3PYI5tWEvJoJUwTZ1Wg== X-Received: from ilnc8.prod.google.com ([2002:a92:dc88:0:b0:500:1d31:d513]) (user=coltonlewis job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6808:1250:b0:479:d779:3544 with SMTP id 5614622812f47-4872f2e1d0fmr2673319b6e.5.1781292555927; Fri, 12 Jun 2026 12:29:15 -0700 (PDT) Date: Fri, 12 Jun 2026 19:28:54 +0000 In-Reply-To: <20260612192909.1153907-1-coltonlewis@google.com> Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260612192909.1153907-1-coltonlewis@google.com> X-Mailer: git-send-email 2.54.0.1136.gdb2ca164c4-goog Message-ID: <20260612192909.1153907-7-coltonlewis@google.com> Subject: [PATCH 06/21] perf: arm_pmuv3: Allocate counter indices from high to low From: Colton Lewis To: kvm@vger.kernel.org Cc: Alexandru Elisei , Paolo Bonzini , Jonathan Corbet , Russell King , Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Mingwei Zhang , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Mark Rutland , Shuah Khan , Ganapatrao Kulkarni , James Clark , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org, Colton Lewis Content-Type: text/plain; charset="UTF-8" To minimize collisions between host and guest counters, allocate host counters from high to low. How the pivot HPMN is defined to partition the counters gives the guest the low index counters. Doing this with index math instead of defining a for_each_set_bit_reverse macro is safe because cntr_mask is always a dense range while the host is running. Signed-off-by: Colton Lewis --- drivers/perf/arm_pmuv3.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index 17bb1cfdc271c..d7a49dc0b0be6 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -953,10 +953,12 @@ static int armv8pmu_get_single_idx(struct pmu_hw_events *cpuc, { int idx; - for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV8_PMU_MAX_GENERAL_COUNTERS) { - if (!test_and_set_bit(idx, cpuc->used_mask)) + for (idx = ARMV8_PMU_MAX_GENERAL_COUNTERS - 1; idx >= 0; idx--) { + if (test_bit(idx, cpu_pmu->cntr_mask) && + !test_and_set_bit(idx, cpuc->used_mask)) return idx; } + return -EAGAIN; } @@ -969,17 +971,22 @@ static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc, * Chaining requires two consecutive event counters, where * the lower idx must be even. */ - for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV8_PMU_MAX_GENERAL_COUNTERS) { + for (idx = ARMV8_PMU_MAX_GENERAL_COUNTERS - 1; idx >= 0; idx--) { if (!(idx & 0x1)) continue; - if (!test_and_set_bit(idx, cpuc->used_mask)) { - /* Check if the preceding even counter is available */ - if (!test_and_set_bit(idx - 1, cpuc->used_mask)) - return idx; - /* Release the Odd counter */ - clear_bit(idx, cpuc->used_mask); + + if (test_bit(idx, cpu_pmu->cntr_mask) && + test_bit(idx - 1, cpu_pmu->cntr_mask)) { + if (!test_and_set_bit(idx, cpuc->used_mask)) { + /* Check if the preceding even counter is available */ + if (!test_and_set_bit(idx - 1, cpuc->used_mask)) + return idx; + /* Release the Odd counter */ + clear_bit(idx, cpuc->used_mask); + } } } + return -EAGAIN; } -- 2.54.0.1136.gdb2ca164c4-goog