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From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Reinette Chatre <reinette.chatre@intel.com>
Cc: shuah@kernel.org, Dave.Martin@arm.com, james.morse@arm.com,
	 tony.luck@intel.com, babu.moger@amd.com, fenghuay@nvidia.com,
	 peternewman@google.com, zide.chen@intel.com,
	dapeng1.mi@linux.intel.com,  ben.horgan@arm.com,
	yu.c.chen@intel.com, linux-kselftest@vger.kernel.org,
	 LKML <linux-kernel@vger.kernel.org>,
	patches@lists.linux.dev
Subject: Re: [PATCH v2 1/9] selftests/resctrl: Improve accuracy of cache occupancy test
Date: Mon, 9 Mar 2026 09:44:01 +0200 (EET)	[thread overview]
Message-ID: <4de9a318-25f3-3a33-50dc-8d8b85930652@linux.intel.com> (raw)
In-Reply-To: <322603c3-24ef-4cd7-bbb5-8d5257256e24@intel.com>

[-- Attachment #1: Type: text/plain, Size: 2897 bytes --]

On Fri, 6 Mar 2026, Reinette Chatre wrote:
> On 3/6/26 1:47 AM, Ilpo Järvinen wrote:
> > On Tue, 3 Mar 2026, Reinette Chatre wrote:
> > 
> >> Dave Martin reported inconsistent CMT test failures. In one experiment
> >> the first run of the CMT test failed because of too large (24%) difference
> >> between measured and achievable cache occupancy while the second run passed
> >> with an acceptable 4% difference.
> >>
> >> The CMT test is susceptible to interference from the rest of the system.
> >> This can be demonstrated with a utility like stress-ng by running the CMT
> >> test while introducing cache misses using:
> >>
> >>    stress-ng --matrix-3d 0 --matrix-3d-zyx
> >>
> >> Below shows an example of the CMT test failing because of a significant
> >> difference between measured and achievable cache occupancy when run with
> >> interference:
> >>     # Starting CMT test ...
> >>     # Mounting resctrl to "/sys/fs/resctrl"
> >>     # Cache size :56623104
> >>     # Writing benchmark parameters to resctrl FS
> >>     # Benchmark PID: 3275
> >>     # Checking for pass/fail
> >>     # Fail: Check cache miss rate within 15%
> >>     # Percent diff=97
> >>     # Number of bits: 5
> >>     # Average LLC val: 501350
> >>     # Cache span (bytes): 23592960
> >>     not ok 1 CMT: test
> >>
> >> The CMT test creates a new control group that is also capable of monitoring
> >> and assigns the workload to it. The workload allocates a buffer that by
> >> default fills a portion of the L3 and keeps reading from the buffer,
> >> measuring the L3 occupancy at intervals. The test passes if the workload's
> >> L3 occupancy is within 15% of the buffer size.
> >>
> >> By not adjusting any capacity bitmasks the workload shares the cache with
> >> the rest of the system. Any other task that may be running could evict
> >> the workload's data from the cache causing it to have low cache occupancy.
> >>
> >> Reduce interference from the rest of the system by ensuring that the
> >> workload's control group uses the capacity bitmask found in the user
> >> parameters for L3 and that the rest of the system can only allocate into
> >> the inverse of the workload's L3 cache portion. Other tasks can thus no
> >> longer evict the workload's data from L3.
> >>
> >> Take the L2 cache into account to further improve test accuracy.
> >> By default the buffer size is the same as the L3 portion that the workload
> >> can allocate into. This buffer size does not take into account that some
> >> of the workload's data may land in L2/L1. Address this in two ways:
> >>  - Reduce the amount of L2 cache the workload can allocate into to the
> > 
> > "into to the" sounds wrong.
> 
> How about:
>   "Reduce the workload's L2 cache allocation to the minimum on systems that
>    support L2 cache allocation."

Works for me.

-- 
 i.

  reply	other threads:[~2026-03-09  7:44 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-04  0:19 [PATCH v2 0/9] selftests/resctrl: Fixes and improvements focused on Intel platforms Reinette Chatre
2026-03-04  0:19 ` [PATCH v2 1/9] selftests/resctrl: Improve accuracy of cache occupancy test Reinette Chatre
2026-03-06  9:47   ` Ilpo Järvinen
2026-03-06 19:24     ` Reinette Chatre
2026-03-09  7:44       ` Ilpo Järvinen [this message]
2026-03-04  0:19 ` [PATCH v2 2/9] selftests/resctrl: Do not store iMC counter value in counter config structure Reinette Chatre
2026-03-06  9:51   ` Ilpo Järvinen
2026-03-06 19:25     ` Reinette Chatre
2026-03-04  0:19 ` [PATCH v2 3/9] selftests/resctrl: Prepare for parsing multiple events per iMC Reinette Chatre
2026-03-04  0:19 ` [PATCH v2 4/9] selftests/resctrl: Support multiple events associated with iMC Reinette Chatre
2026-03-06 10:18   ` Ilpo Järvinen
2026-03-06 19:25     ` Reinette Chatre
2026-03-04  0:19 ` [PATCH v2 5/9] selftests/resctrl: Increase size of buffer used in MBM and MBA tests Reinette Chatre
2026-03-04  0:19 ` [PATCH v2 6/9] selftests/resctrl: Raise threshold at which MBM and PMU values are compared Reinette Chatre
2026-03-04  0:19 ` [PATCH v2 7/9] selftests/resctrl: Remove requirement on cache miss rate Reinette Chatre
2026-03-04  0:19 ` [PATCH v2 8/9] selftests/resctrl: Simplify perf usage in CAT test Reinette Chatre
2026-03-04  0:19 ` [PATCH v2 9/9] selftests/resctrl: Reduce L2 impact on " Reinette Chatre
2026-03-06 10:35   ` Ilpo Järvinen
2026-03-06 19:26     ` Reinette Chatre
2026-03-04 15:18 ` [PATCH v2 0/9] selftests/resctrl: Fixes and improvements focused on Intel platforms Chen, Yu C

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