From: Reinette Chatre <reinette.chatre@intel.com>
To: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Cc: <shuah@kernel.org>, <Dave.Martin@arm.com>, <james.morse@arm.com>,
<tony.luck@intel.com>, <babu.moger@amd.com>,
<fenghuay@nvidia.com>, <peternewman@google.com>,
<zide.chen@intel.com>, <dapeng1.mi@linux.intel.com>,
<ben.horgan@arm.com>, <yu.c.chen@intel.com>,
<jason.zeng@intel.com>, <linux-kselftest@vger.kernel.org>,
LKML <linux-kernel@vger.kernel.org>, <patches@lists.linux.dev>
Subject: Re: [PATCH v3 10/10] selftests/resctrl: Reduce L2 impact on CAT test
Date: Fri, 27 Mar 2026 16:22:29 -0700 [thread overview]
Message-ID: <71fe5d8c-3ff1-40ee-b4de-522a5a7b4195@intel.com> (raw)
In-Reply-To: <afefcfb5-3f6a-6d6d-976e-c10dcaa61abb@linux.intel.com>
Hi Ilpo,
On 3/27/26 10:49 AM, Ilpo Järvinen wrote:
> On Fri, 13 Mar 2026, Reinette Chatre wrote:
>
>> The L3 CAT test loads a buffer into cache that is proportional to the L3
>> size allocated for the workload and measures cache misses when accessing
>> the buffer as a test of L3 occupancy. When loading the buffer it can be
>> assumed that a portion of the buffer will be loaded into the L2 cache and
>> depending on cache design may not be present in L3. It is thus possible
>> for data to not be in L3 but also not trigger an L3 cache miss when
>> accessed.
>>
>> Reduce impact of L2 on the L3 CAT test by, if L2 allocation is supported,
>> minimizing the portion of L2 that the workload can allocate into. This
>> encourages most of buffer to be loaded into L3 and support better
>> comparison between buffer size, cache portion, and cache misses when
>> accessing the buffer.
>>
>> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
>> Tested-by: Chen Yu <yu.c.chen@intel.com>
>> ---
>> Changes since v2:
>> - Add Chen Yu's tag.
>> ---
>> tools/testing/selftests/resctrl/cat_test.c | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/selftests/resctrl/cat_test.c
>> index 6aac03147d41..371a2f26dc47 100644
>> --- a/tools/testing/selftests/resctrl/cat_test.c
>> +++ b/tools/testing/selftests/resctrl/cat_test.c
>> @@ -157,6 +157,10 @@ static int cat_test(const struct resctrl_test *test,
>> if (ret)
>> goto reset_affinity;
>>
>> + ret = minimize_l2_occupancy(test, uparams, param);
>> + if (ret)
>> + goto reset_affinity;
>> +
>> perf_event_attr_initialize(&pea, PERF_COUNT_HW_CACHE_MISSES);
>> pe_fd = perf_open(&pea, bm_pid, uparams->cpu);
>> if (pe_fd < 0) {
>>
>
> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
>
Thank you very much for this and all the other reviews. Much appreciated.
Reinette
next prev parent reply other threads:[~2026-03-27 23:23 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-13 20:32 [PATCH v3 00/10] selftests/resctrl: Fixes and improvements focused on Intel platforms Reinette Chatre
2026-03-13 20:32 ` [PATCH v3 01/10] selftests/resctrl: Improve accuracy of cache occupancy test Reinette Chatre
2026-03-26 12:44 ` Ilpo Järvinen
2026-03-13 20:32 ` [PATCH v3 02/10] selftests/resctrl: Reduce interference from L2 occupancy during " Reinette Chatre
2026-03-26 12:56 ` Ilpo Järvinen
2026-03-13 20:32 ` [PATCH v3 03/10] selftests/resctrl: Do not store iMC counter value in counter config structure Reinette Chatre
2026-03-13 20:32 ` [PATCH v3 04/10] selftests/resctrl: Prepare for parsing multiple events per iMC Reinette Chatre
2026-03-26 13:03 ` Ilpo Järvinen
2026-03-26 14:34 ` Reinette Chatre
2026-03-13 20:32 ` [PATCH v3 05/10] selftests/resctrl: Support multiple events associated with iMC Reinette Chatre
2026-03-27 17:28 ` Ilpo Järvinen
2026-03-13 20:32 ` [PATCH v3 06/10] selftests/resctrl: Increase size of buffer used in MBM and MBA tests Reinette Chatre
2026-03-27 17:30 ` Ilpo Järvinen
2026-03-13 20:32 ` [PATCH v3 07/10] selftests/resctrl: Raise threshold at which MBM and PMU values are compared Reinette Chatre
2026-03-27 17:34 ` Ilpo Järvinen
2026-03-27 23:19 ` Reinette Chatre
2026-03-13 20:32 ` [PATCH v3 08/10] selftests/resctrl: Remove requirement on cache miss rate Reinette Chatre
2026-03-27 17:45 ` Ilpo Järvinen
2026-03-27 23:21 ` Reinette Chatre
2026-03-31 8:07 ` Ilpo Järvinen
2026-03-31 17:39 ` Reinette Chatre
2026-03-13 20:32 ` [PATCH v3 09/10] selftests/resctrl: Simplify perf usage in CAT test Reinette Chatre
2026-03-27 17:47 ` Ilpo Järvinen
2026-03-13 20:32 ` [PATCH v3 10/10] selftests/resctrl: Reduce L2 impact on " Reinette Chatre
2026-03-27 17:49 ` Ilpo Järvinen
2026-03-27 23:22 ` Reinette Chatre [this message]
2026-03-31 19:13 ` [PATCH v3 00/10] selftests/resctrl: Fixes and improvements focused on Intel platforms Shuah Khan
2026-03-31 20:22 ` Reinette Chatre
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