From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2284155A30; Wed, 20 Aug 2025 22:24:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755728667; cv=none; b=gZl0A0mjWsA1pwtozyH7cg8557X/WyerRJxqu1SBoUohgj2MPvTyAI9fFJOfXEnGuHZ1+5nTSuhUSbtKPji0FZhND5a9b/433GPZfDORLByZ2axPth0Wl6fPO7xrcieadJMK2yh4hLcBi/A0QaSHgKxQtlO4QsM0MUfODDR8Kro= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755728667; c=relaxed/simple; bh=ysNe3rGWwElNFQFScxZngEi0VfXeoQjX5AlbYef/6wk=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=T8u0hebVoBHlWTlCDDDCuQwYIVbuSPZDJ+X9BhIimhfkSlIIyzDYOSzipoyPFBn329O7oCIHPSxqfqz19ERcld22M08GPpsX+eVTUi8Qn3qTM7Fwbp/NWTNDbEC2ucZq3wIJ+1siPqq6MIRhTf7wDE0TNymcwNZoVy9NGNm7A2A= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=E0LHqwsB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="E0LHqwsB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 346C4C4CEE7; Wed, 20 Aug 2025 22:24:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755728667; bh=ysNe3rGWwElNFQFScxZngEi0VfXeoQjX5AlbYef/6wk=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=E0LHqwsB/FLhEq23DaO6O76nUZpFqFY5BwK9BXZi06/G/EzcYm081Mx6tA99iCfDS eOCG+JnnXDq13atuzO5CYJqlEDjZcJPBgcDgXNuSpxl4GFINUKHRU59cXTCoWSa2g1 zTGQbt/gpVGni5/XJ6N2eHClmVLY94gnyl1QoV7/Drc/es+LQ2BEj6q5aNOj0D/EGj ugqr+4JHh6jdnCxol72zTj/IpkmB9/B/BHiMu0wXj0YzE4f3x5FilwetESXcJ+esEJ LVDGcT9VcITtewtQAX0hhlsonOF/6/UiX+afEspBp/YTqZygiPQ/CTIQbI78cLfpnO H2KYQEt+MC+IA== Received: from host86-149-246-145.range86-149.btcentralplus.com ([86.149.246.145] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uorEH-009W7G-8x; Wed, 20 Aug 2025 23:24:25 +0100 Date: Wed, 20 Aug 2025 23:24:24 +0100 Message-ID: <87ikihk4x3.wl-maz@kernel.org> From: Marc Zyngier To: Mark Brown Cc: Catalin Marinas , Will Deacon , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v15 1/6] arm64/gcs: Ensure FGTs for EL1 GCS instructions are disabled In-Reply-To: <20250820-arm64-gcs-v15-1-5e334da18b84@kernel.org> References: <20250820-arm64-gcs-v15-0-5e334da18b84@kernel.org> <20250820-arm64-gcs-v15-1-5e334da18b84@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 86.149.246.145 X-SA-Exim-Rcpt-To: broonie@kernel.org, catalin.marinas@arm.com, will@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, shuah@kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Wed, 20 Aug 2025 15:14:41 +0100, Mark Brown wrote: > > The initial EL2 setup for GCS did not include disabling of EL1 usage of > GCS instructions, also disable these traps. This is the first disabling > of instruction traps, use x2 to store the value to be written. Written where? > > Signed-off-by: Mark Brown > --- > arch/arm64/include/asm/el2_setup.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h > index 46033027510c..0ac14ea4dbc8 100644 > --- a/arch/arm64/include/asm/el2_setup.h > +++ b/arch/arm64/include/asm/el2_setup.h > @@ -355,6 +355,10 @@ > > .Lskip_gce_fgt_\@: > > + orr x2, x2, #HFGITR_EL2_nGCSEPP_MASK What is x2 set to before this? > + orr x2, x2, #HFGITR_EL2_nGCSSTR_EL1_MASK > + orr x2, x2, #HFGITR_EL2_nGCSPUSHM_EL1_MASK > + > .Lset_fgt_\@: > msr_s SYS_HFGRTR_EL2, x0 > msr_s SYS_HFGWTR_EL2, x0 Followed by: msr_s SYS_HFGITR_EL2, xzr Puzzled. M. -- Jazz isn't dead. It just smells funny.