From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B3282D6E73; Wed, 20 Aug 2025 21:07:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755724022; cv=none; b=tzm9/zdJHaMb9bWzwFJmnmFQ0H9UKo5NgDKso7vrFeEtv3aHVAXtW/FjJgRM8cjc4ve9YQm4dzKX4/ANpGBW06QAbCpUtkuIOgmQKy9H82uWfcjOmgoZ0kjr9V7tnjWmmyvNxVjXg0ySvvA5fMN8HXjD19waDX9dF6xyXndXjec= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755724022; c=relaxed/simple; bh=jEpv9dsCIXbIBynicqQ0dP6JZ4BCvS3IdZffu8Qg+1c=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=CsChmeb0xLG3NTvq+wsp93KbIQjNyeDub+btos4t6S0cr0nVRIUGVuuKbpIUjvJEV4X81NTtzGWcTdQSZC5/uLW3Ia5FuEPTsQ3NIFcHim4vXeoJUqtsHWlq18f/OMHNUByx8wsMS6gaLthTdSG9CxHzQ0+Aa77oufy0rKn8qqk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=G3oP929V; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="G3oP929V" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8D48BC4CEE7; Wed, 20 Aug 2025 21:07:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755724021; bh=jEpv9dsCIXbIBynicqQ0dP6JZ4BCvS3IdZffu8Qg+1c=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=G3oP929VN3mOReD4gapeeAz0APdZitM87mRHUoIrjvMqRBGT36c6TO0Q3kssDHFAI OJQ6I2iZQ16iz7g5jbqvGFUnvGCB6RNF+N4zksRA/la3qiQGoqikYBAuXnmZxkQlnS 056xF1PYZfrDayO79EvbOieHqwirJwJNMvvLRdjhkwRtThNRthQM1qf3pcYoFpmH9K X1rmyjauvh1/DXMkzV8qGancHdH8Di01ZfckFRu9YhrBYsgEYc0JaDURG+2yTTjL/G G9LWDRv76Q+x6xkbK5f7FmrxjEplH2dIE0GkpS0DBjKMFauFuVCdmctRXf6do+E3Ee f4K1/rxpexnqA== Received: from host86-149-246-145.range86-149.btcentralplus.com ([86.149.246.145] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uoq1C-009V23-Nf; Wed, 20 Aug 2025 22:06:51 +0100 Date: Wed, 20 Aug 2025 22:06:49 +0100 Message-ID: <87o6s9k8ie.wl-maz@kernel.org> From: Marc Zyngier To: Mark Brown Cc: Catalin Marinas , Will Deacon , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v15 2/6] KVM: arm64: Manage GCS access and registers for guests In-Reply-To: <20250820-arm64-gcs-v15-2-5e334da18b84@kernel.org> References: <20250820-arm64-gcs-v15-0-5e334da18b84@kernel.org> <20250820-arm64-gcs-v15-2-5e334da18b84@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 86.149.246.145 X-SA-Exim-Rcpt-To: broonie@kernel.org, catalin.marinas@arm.com, will@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, shuah@kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Wed, 20 Aug 2025 15:14:42 +0100, Mark Brown wrote: > > GCS introduces a number of system registers for EL1 and EL0, on systems and EL2. > with GCS we need to context switch them and expose them to VMMs to allow > guests to use GCS. > > In order to allow guests to use GCS we also need to configure > HCRX_EL2.GCSEn, if this is not set GCS instructions will be noops and > CHKFEAT will report GCS as disabled. Also enable fine grained traps for > access to the GCS registers by guests which do not have the feature > enabled. I don't see any FGT configuration in this patch. As far as I can tell, the FGU generation already takes care of that particular case. > > In order to allow userspace to control availability of the feature to > guests we enable writability for only ID_AA64PFR1_EL1.GCS, this is a > deliberately conservative choice to avoid errors due to oversights. > Further fields should be made writable in future. I'm not sure what you mean by that. Making the feature field writable is only allowable if we have some level of support (and otherwise we should prevent both the feature being exposed, and the field being writable). So future fields being writable will only happen when the features are fully supported, and only then. Please clarify, or drop this altogether. > > Signed-off-by: Mark Brown > --- > arch/arm64/include/asm/kvm_emulate.h | 3 +++ > arch/arm64/include/asm/kvm_host.h | 14 ++++++++++++++ > arch/arm64/include/asm/vncr_mapping.h | 2 ++ > arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 31 ++++++++++++++++++++++++++++++ > arch/arm64/kvm/hyp/vhe/sysreg-sr.c | 10 ++++++++++ > arch/arm64/kvm/sys_regs.c | 31 +++++++++++++++++++++++++++++- > 6 files changed, 90 insertions(+), 1 deletion(-) > [...] > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 82ffb3b3b3cf..592cb5d6497a 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -138,6 +138,8 @@ static bool get_el2_to_el1_mapping(unsigned int reg, > MAPPED_EL2_SYSREG(PIR_EL2, PIR_EL1, NULL ); > MAPPED_EL2_SYSREG(PIRE0_EL2, PIRE0_EL1, NULL ); > MAPPED_EL2_SYSREG(POR_EL2, POR_EL1, NULL ); > + MAPPED_EL2_SYSREG(GCSCR_EL2, GCSCR_EL1, NULL ); > + MAPPED_EL2_SYSREG(GCSPR_EL2, GCSPR_EL1, NULL ); How is the state accessed when loaded on the CPU? You seem to be missing accessors for these two registers, affecting both EL1 and EL2 in the guest. M. -- Jazz isn't dead. It just smells funny.