From: Jesse Taube <jesse@rivosinc.com>
To: linux-riscv@lists.infradead.org
Cc: "Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Alexandre Ghiti" <alex@ghiti.fr>,
"Oleg Nesterov" <oleg@redhat.com>, "Kees Cook" <kees@kernel.org>,
"Peter Zijlstra" <peterz@infradead.org>,
"Ingo Molnar" <mingo@redhat.com>,
"Arnaldo Carvalho de Melo" <acme@kernel.org>,
"Namhyung Kim" <namhyung@kernel.org>,
"Mark Rutland" <mark.rutland@arm.com>,
"Alexander Shishkin" <alexander.shishkin@linux.intel.com>,
"Jiri Olsa" <jolsa@kernel.org>, "Ian Rogers" <irogers@google.com>,
"Adrian Hunter" <adrian.hunter@intel.com>,
"Liang Kan" <kan.liang@linux.intel.com>,
"Shuah Khan" <shuah@kernel.org>,
"Himanshu Chauhan" <hchauhan@ventanamicro.com>,
"Charlie Jenkins" <charlie@rivosinc.com>,
"Samuel Holland" <samuel.holland@sifive.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Deepak Gupta" <debug@rivosinc.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Atish Patra" <atishp@rivosinc.com>,
"Anup Patel" <apatel@ventanamicro.com>,
"Mayuresh Chitale" <mchitale@ventanamicro.com>,
"Evan Green" <evan@rivosinc.com>,
WangYuli <wangyuli@uniontech.com>,
"Huacai Chen" <chenhuacai@kernel.org>,
"Arnd Bergmann" <arnd@arndb.de>,
"Andrew Morton" <akpm@linux-foundation.org>,
"Luis Chamberlain" <mcgrof@kernel.org>,
"Mike Rapoport (Microsoft)" <rppt@kernel.org>,
"Nam Cao" <namcao@linutronix.de>,
"Yunhui Cui" <cuiyunhui@bytedance.com>,
"Joel Granados" <joel.granados@kernel.org>,
"Clément Léger" <cleger@rivosinc.com>,
"Sebastian Andrzej Siewior" <bigeasy@linutronix.de>,
"Celeste Liu" <coelacanthushex@gmail.com>,
"Chunyan Zhang" <zhangchunyan@iscas.ac.cn>,
"Nylon Chen" <nylon.chen@sifive.com>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Thomas Weißschuh" <thomas.weissschuh@linutronix.de>,
"Vincenzo Frascino" <vincenzo.frascino@arm.com>,
"Joey Gouly" <joey.gouly@arm.com>,
"Ravi Bangoria" <ravi.bangoria@amd.com>,
linux-kernel@vger.kernel.org, linux-mm@kvack.org,
linux-perf-users@vger.kernel.org,
linux-kselftest@vger.kernel.org, "Joel Stanley" <joel@jms.id.au>
Subject: Re: [PATCH 0/8] riscv: add initial support for hardware breakpoints
Date: Fri, 22 Aug 2025 10:59:47 -0700 [thread overview]
Message-ID: <CALSpo=aQyb+E0HHDRoXs0f5vvxJtMpCA546ROkq0e3B-ur9QBg@mail.gmail.com> (raw)
In-Reply-To: <20250822174715.1269138-1-jesse@rivosinc.com>
On Fri, Aug 22, 2025 at 10:47 AM Jesse Taube <jesse@rivosinc.com> wrote:
>
> This patchset adds initial support for hardware breakpoints and
> watchpoints to the RISC-V architecture. The framework is built on
> top of perf subsystem and SBI debug trigger extension.
>
> Currently following features are not supported and are in works:
> - icount for single stepping
> - Virtualization of debug triggers
> - kernel space debug triggers
>
> The SBI debug trigger extension can be found at:
> https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/src/ext-debug-triggers.adoc
>
> The Sdtrig ISA is part of RISC-V debug specification which can be
> found at:
> https://github.com/riscv/riscv-debug-spec
>
> based off the original RFC by Himanshu Chauhan here:
> https://lore.kernel.org/lkml/20240222125059.13331-1-hchauhan@ventanamicro.com/
>
> Second RFC by Jesse Taube here:
> https://lore.kernel.org/lkml/20250722173829.984082-1-jesse@rivosinc.com/
>
> Himanshu Chauhan (2):
> riscv: Add SBI debug trigger extension and function ids
> riscv: Introduce support for hardware break/watchpoints
>
> Jesse Taube (6):
> riscv: Add insn.c, consolidate instruction decoding
> riscv: insn: Add get_insn_nofault
> riscv: hw_breakpoint: Use icount for single stepping
> riscv: ptrace: Add hw breakpoint support
> riscv: ptrace: Add hw breakpoint regset
> selftests: riscv: Add test for hardware breakpoints
>
> arch/riscv/Kconfig | 2 +
> arch/riscv/include/asm/bug.h | 12 -
> arch/riscv/include/asm/hw_breakpoint.h | 59 ++
> arch/riscv/include/asm/insn.h | 132 ++-
> arch/riscv/include/asm/kdebug.h | 3 +-
> arch/riscv/include/asm/processor.h | 4 +
> arch/riscv/include/asm/sbi.h | 33 +-
> arch/riscv/include/uapi/asm/ptrace.h | 9 +
> arch/riscv/kernel/Makefile | 2 +
> arch/riscv/kernel/hw_breakpoint.c | 763 ++++++++++++++++++
> arch/riscv/kernel/insn.c | 165 ++++
> arch/riscv/kernel/kgdb.c | 102 +--
> arch/riscv/kernel/probes/kprobes.c | 1 +
> arch/riscv/kernel/process.c | 4 +
> arch/riscv/kernel/ptrace.c | 169 ++++
> arch/riscv/kernel/traps.c | 11 +-
> arch/riscv/kernel/traps_misaligned.c | 93 +--
> include/uapi/linux/elf.h | 2 +
> tools/include/uapi/linux/elf.h | 1 +
> tools/perf/tests/tests.h | 3 +-
> tools/testing/selftests/riscv/Makefile | 2 +-
> .../selftests/riscv/breakpoints/.gitignore | 1 +
> .../selftests/riscv/breakpoints/Makefile | 13 +
> .../riscv/breakpoints/breakpoint_test.c | 246 ++++++
> 24 files changed, 1641 insertions(+), 191 deletions(-)
> create mode 100644 arch/riscv/include/asm/hw_breakpoint.h
> create mode 100644 arch/riscv/kernel/hw_breakpoint.c
> create mode 100644 arch/riscv/kernel/insn.c
> create mode 100644 tools/testing/selftests/riscv/breakpoints/.gitignore
> create mode 100644 tools/testing/selftests/riscv/breakpoints/Makefile
> create mode 100644 tools/testing/selftests/riscv/breakpoints/breakpoint_test.c
>
> --
> 2.43.0
>
Oops, this meant to be V2.
Thanks,
Jesse Taube
next prev parent reply other threads:[~2025-08-22 17:59 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-22 17:47 [PATCH 0/8] riscv: add initial support for hardware breakpoints Jesse Taube
2025-08-22 17:47 ` [PATCH 1/8] riscv: Add insn.c, consolidate instruction decoding Jesse Taube
2025-08-24 14:52 ` Anup Patel
2025-08-22 17:47 ` [PATCH 2/8] riscv: Add SBI debug trigger extension and function ids Jesse Taube
2025-08-22 17:47 ` [PATCH 3/8] riscv: insn: Add get_insn_nofault Jesse Taube
2025-08-22 17:47 ` [PATCH 4/8] riscv: Introduce support for hardware break/watchpoints Jesse Taube
2025-09-02 5:13 ` Qingfang Deng
2025-08-22 17:47 ` [PATCH 5/8] riscv: hw_breakpoint: Use icount for single stepping Jesse Taube
2025-08-26 4:38 ` Himanshu Chauhan
2025-08-27 8:04 ` Charlie Jenkins
2025-08-28 17:46 ` Jesse T
2025-08-22 17:47 ` [PATCH 6/8] riscv: ptrace: Add hw breakpoint support Jesse Taube
2025-08-22 17:47 ` [PATCH 7/8] riscv: ptrace: Add hw breakpoint regset Jesse Taube
2025-08-22 17:47 ` [PATCH 8/8] selftests: riscv: Add test for hardware breakpoints Jesse Taube
2025-08-22 17:59 ` Jesse Taube [this message]
-- strict thread matches above, loose matches on Subject: below --
2025-08-05 19:39 [PATCH 0/8] riscv: add initial support " Jesse Taube
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