From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8257C433F5 for ; Thu, 10 Feb 2022 11:39:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235635AbiBJLjK (ORCPT ); Thu, 10 Feb 2022 06:39:10 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:41226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241059AbiBJLjJ (ORCPT ); Thu, 10 Feb 2022 06:39:09 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A13B91019 for ; Thu, 10 Feb 2022 03:39:10 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 3CBA261D16 for ; Thu, 10 Feb 2022 11:39:10 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B8A8CC004E1; Thu, 10 Feb 2022 11:39:06 +0000 (UTC) Date: Thu, 10 Feb 2022 11:39:03 +0000 From: Catalin Marinas To: Mark Brown Cc: Will Deacon , Marc Zyngier , Shuah Khan , Shuah Khan , Alan Hayward , Luis Machado , Salil Akerkar , Basant Kumar Dwivedi , Szabolcs Nagy , James Morse , Alexandru Elisei , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, kvmarm@lists.cs.columbia.edu Subject: Re: [PATCH v11 03/40] arm64: cpufeature: Always specify and use a field width for capabilities Message-ID: References: <20220207152109.197566-1-broonie@kernel.org> <20220207152109.197566-4-broonie@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220207152109.197566-4-broonie@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org On Mon, Feb 07, 2022 at 03:20:32PM +0000, Mark Brown wrote: > Since all the fields in the main ID registers are 4 bits wide we have up > until now not bothered specifying the width in the code. Since we now > wish to use this mechanism to enumerate features from the floating point > feature registers which do not follow this pattern add a width to the > table. This means updating all the existing table entries but makes it > less likely that we run into issues in future due to implicitly assuming > a 4 bit width. > > Signed-off-by: Mark Brown > Cc: Suzuki K Poulose > --- > arch/arm64/include/asm/cpufeature.h | 1 + > arch/arm64/kernel/cpufeature.c | 167 +++++++++++++++++----------- > 2 files changed, 102 insertions(+), 66 deletions(-) I know it's a positive diffstat but I prefer being explicit with the field width. So: Reviewed-by: Catalin Marinas