From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C318AC433F5 for ; Wed, 2 Mar 2022 11:52:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229971AbiCBLxk (ORCPT ); Wed, 2 Mar 2022 06:53:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237334AbiCBLxj (ORCPT ); Wed, 2 Mar 2022 06:53:39 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 833C448E6D for ; Wed, 2 Mar 2022 03:52:56 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1F49D618A2 for ; Wed, 2 Mar 2022 11:52:56 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EE279C004E1; Wed, 2 Mar 2022 11:52:52 +0000 (UTC) Date: Wed, 2 Mar 2022 11:52:49 +0000 From: Catalin Marinas To: Marc Zyngier Cc: Qian Cai , Mark Brown , Will Deacon , Shuah Khan , Shuah Khan , Basant Kumar Dwivedi , Luis Machado , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kselftest@vger.kernel.org, Alan Hayward , kvmarm@lists.cs.columbia.edu, Salil Akerkar Subject: Re: [PATCH v11 03/40] arm64: cpufeature: Always specify and use a field width for capabilities Message-ID: References: <20220207152109.197566-1-broonie@kernel.org> <20220207152109.197566-4-broonie@kernel.org> <878rts3bpi.wl-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <878rts3bpi.wl-maz@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org On Wed, Mar 02, 2022 at 10:12:09AM +0000, Marc Zyngier wrote: > On Tue, 01 Mar 2022 22:56:41 +0000, > Qian Cai wrote: > > > > On Mon, Feb 07, 2022 at 03:20:32PM +0000, Mark Brown wrote: > > > Since all the fields in the main ID registers are 4 bits wide we have up > > > until now not bothered specifying the width in the code. Since we now > > > wish to use this mechanism to enumerate features from the floating point > > > feature registers which do not follow this pattern add a width to the > > > table. This means updating all the existing table entries but makes it > > > less likely that we run into issues in future due to implicitly assuming > > > a 4 bit width. > > > > > > Signed-off-by: Mark Brown > > > > Do we leave this one alone on purpose? > > > > .desc = "GIC system register CPU interface", > > .capability = ARM64_HAS_SYSREG_GIC_CPUIF, > > .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, > > .matches = has_useable_gicv3_cpuif, > > .sys_reg = SYS_ID_AA64PFR0_EL1, > > .field_pos = ID_AA64PFR0_GIC_SHIFT, > > .sign = FTR_UNSIGNED, > > .min_field_value = 1, > > > > Since width == 0, it will generate an undefined behavior. > > I don't think that's on purpose, and we should definitely address > this. Maybe we should have a warning if we spot an occurrence of > .width being 0. We should indeed have a check. Alternatively, assume the default to be 4 and convert all 0s to 4 during boot (less patch churn). -- Catalin