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AJvYcCWcOohMySZ+UFqVyc3P6FBiU2bXbtfLYcdWV+lAJ5acNTkHfzxj7aUzCNehuc7BWtGks2l2/BkAHkGE/gyJKrI=@vger.kernel.org X-Gm-Message-State: AOJu0YycHdTxQYPPhE86awZ0uYDknOv/cP8LIrpye3I8XyppFQp40TXS SkaQ++agD0EEYw3Ccp26IpF3GwCC61bLb1ZSc/nmn8q23dxg5JjFXqIlBzp7NnP1y30bZfeeMZ7 bng== X-Google-Smtp-Source: AGHT+IGNfKCZ8Q2VCeggXdXbou0bzD5z1DgxcTPhkKTSHTkFCJPodqXfpK8DgQ73ma5DxN7hfHcC0Lc1R+c= X-Received: from pfbf7.prod.google.com ([2002:a05:6a00:ad87:b0:725:c96b:b1db]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a20:d81a:b0:1e3:e6f3:6372 with SMTP id adf61e73a8af0-1e88d132ef8mr6644654637.27.1736365365004; Wed, 08 Jan 2025 11:42:45 -0800 (PST) Date: Wed, 8 Jan 2025 11:42:43 -0800 In-Reply-To: <20240918205319.3517569-7-coltonlewis@google.com> Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240918205319.3517569-1-coltonlewis@google.com> <20240918205319.3517569-7-coltonlewis@google.com> Message-ID: Subject: Re: [PATCH v2 6/6] KVM: x86: selftests: Test PerfMonV2 From: Sean Christopherson To: Colton Lewis Cc: kvm@vger.kernel.org, Mingwei Zhang , Jinrong Liang , Jim Mattson , Aaron Lewis , Paolo Bonzini , Shuah Khan , linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" On Wed, Sep 18, 2024, Colton Lewis wrote: > Test PerfMonV2, which defines global registers to enable multiple > performance counters with a single MSR write, in its own function. > > If the feature is available, ensure the global control register has > the ability to start and stop the performance counters and the global > status register correctly flags an overflow by the associated counter. > > Signed-off-by: Colton Lewis > --- > .../selftests/kvm/x86_64/pmu_counters_test.c | 53 +++++++++++++++++++ > 1 file changed, 53 insertions(+) > > diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c > index cf2941cc7c4c..a90df8b67a19 100644 > --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c > +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c > @@ -763,10 +763,63 @@ static void guest_test_core_events(void) > } > } > > +static void guest_test_perfmon_v2(void) > +{ > + uint64_t i; > + uint64_t eventsel = ARCH_PERFMON_EVENTSEL_OS | > + ARCH_PERFMON_EVENTSEL_ENABLE | > + AMD_ZEN_CORE_CYCLES; Hmm. I like the extra coverage, but I think the guts of this test belong is common code, because the core logic is the same across Intel and AMD (I think), only the MSRs are different. Maybe a library helper that takes in the MSRs as parameters? Not sure. I suspect it'll take some back and forth to figure out how best to validate these more "advanced" behaviors, so maybe skip this patch for the next version? I.e. land basic AMD coverage and then we can figure out how to test global control and status. > + bool core_ext = this_cpu_has(X86_FEATURE_PERF_CTR_EXT_CORE); > + uint64_t sel_msr_base = core_ext ? MSR_F15H_PERF_CTL : MSR_K7_EVNTSEL0; > + uint64_t cnt_msr_base = core_ext ? MSR_F15H_PERF_CTR : MSR_K7_PERFCTR0; > + uint64_t msr_step = core_ext ? 2 : 1; > + uint8_t nr_counters = guest_nr_core_counters(); > + bool perfmon_v2 = this_cpu_has(X86_FEATURE_PERFMON_V2); Zero reason to capture this in a local variable. > + uint64_t sel_msr; > + uint64_t cnt_msr; > + > + if (!perfmon_v2) > + return; > + > + for (i = 0; i < nr_counters; i++) { > + sel_msr = sel_msr_base + msr_step * i; > + cnt_msr = cnt_msr_base + msr_step * i; > + > + /* Ensure count stays 0 when global register disables counter. */ > + wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0); > + wrmsr(sel_msr, eventsel); > + wrmsr(cnt_msr, 0); > + __asm__ __volatile__("loop ." : "+c"((int){NUM_LOOPS})); > + GUEST_ASSERT(!_rdpmc(i)); > + > + /* Ensure counter is >0 when global register enables counter. */ > + wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, BIT_ULL(i)); > + __asm__ __volatile__("loop ." : "+c"((int){NUM_LOOPS})); > + wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0); > + GUEST_ASSERT(_rdpmc(i)); > + > + /* Ensure global status register flags a counter overflow. */ > + wrmsr(cnt_msr, -1); > + wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, 0xff); > + wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, BIT_ULL(i)); > + __asm__ __volatile__("loop ." : "+c"((int){NUM_LOOPS})); > + wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0); > + GUEST_ASSERT(rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS) & > + BIT_ULL(i)); > + > + /* Ensure global status register flag is cleared correctly. */ > + wrmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, BIT_ULL(i)); > + GUEST_ASSERT(!(rdmsr(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS) & > + BIT_ULL(i))); > + } > +} > + > + > static void guest_test_core_counters(void) > { > guest_test_rdwr_core_counters(); > guest_test_core_events(); > + guest_test_perfmon_v2(); > GUEST_DONE(); > } > > -- > 2.46.0.662.g92d0881bb0-goog >