From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D7623D0AC; Thu, 7 Dec 2023 14:08:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4D40BC433C7; Thu, 7 Dec 2023 14:08:32 +0000 (UTC) Date: Thu, 7 Dec 2023 14:08:29 +0000 From: Catalin Marinas To: Joey Gouly Cc: linux-arm-kernel@lists.infradead.org, akpm@linux-foundation.org, aneesh.kumar@linux.ibm.com, broonie@kernel.org, dave.hansen@linux.intel.com, maz@kernel.org, oliver.upton@linux.dev, shuah@kernel.org, will@kernel.org, kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, James Morse , Suzuki K Poulose , Zenghui Yu Subject: Re: [PATCH v3 07/25] arm64: enable the Permission Overlay Extension for EL0 Message-ID: References: <20231124163510.1835740-1-joey.gouly@arm.com> <20231124163510.1835740-8-joey.gouly@arm.com> Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231124163510.1835740-8-joey.gouly@arm.com> On Fri, Nov 24, 2023 at 04:34:52PM +0000, Joey Gouly wrote: > +#ifdef CONFIG_ARM64_POE > +static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) > +{ > + sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1x_E0POE); > + sysreg_clear_set(CPACR_EL1, 0, CPACR_ELx_E0POE); > +} > +#endif Don't we need the TCR2_EL1x.POE bit (for EL1) enabled as well? I'm thinking of the LDXR/STXR instructions accessing user memory (the futex code). -- Catalin