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AJvYcCUpI3rvZWpuKFzK8eMqLvwFlVh7zIb6NQREm0MVFs9CBrc3NkLMplDNEupWUBrKEGwTzLSJbbGAFieuz6QFKqOzZTJut+fxrcR1UhkKxs2y X-Gm-Message-State: AOJu0YzHLTiezidOp7rtZZfykfamniERZJuwKa5i94QDPw6neTLglRK5 WfF+UgaFbxAMzQ1ygYilIAB74fNgHA4+irWn50pRsERySzVN8TQ8SosNDlnvHr4= X-Google-Smtp-Source: AGHT+IF+cB/VeeNmDI2ko+dsDxMtMfecI39OIzLFhWWIUSbrZvt3Adce25QglCrrCpHnBQogkCEnLA== X-Received: by 2002:a05:6a20:1053:b0:1a9:22cc:3ed4 with SMTP id adf61e73a8af0-1afde0a993fmr4462882637.6.1715380657060; Fri, 10 May 2024 15:37:37 -0700 (PDT) Received: from ghost ([2601:647:5700:6860:629e:3f2:f321:6c]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2b62886b72fsm5609203a91.31.2024.05.10.15.37.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 May 2024 15:37:36 -0700 (PDT) Date: Fri, 10 May 2024 15:37:32 -0700 From: Charlie Jenkins To: Deepak Gupta Cc: paul.walmsley@sifive.com, rick.p.edgecombe@intel.com, broonie@kernel.org, Szabolcs.Nagy@arm.com, kito.cheng@sifive.com, keescook@chromium.org, ajones@ventanamicro.com, conor.dooley@microchip.com, cleger@rivosinc.com, atishp@atishpatra.org, alex@ghiti.fr, bjorn@rivosinc.com, alexghiti@rivosinc.com, samuel.holland@sifive.com, conor@kernel.org, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-kselftest@vger.kernel.org, corbet@lwn.net, palmer@dabbelt.com, aou@eecs.berkeley.edu, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, oleg@redhat.com, akpm@linux-foundation.org, arnd@arndb.de, ebiederm@xmission.com, Liam.Howlett@oracle.com, vbabka@suse.cz, lstoakes@gmail.com, shuah@kernel.org, brauner@kernel.org, andy.chiu@sifive.com, jerry.shih@sifive.com, hankuan.chen@sifive.com, greentime.hu@sifive.com, evan@rivosinc.com, xiao.w.wang@intel.com, apatel@ventanamicro.com, mchitale@ventanamicro.com, dbarboza@ventanamicro.com, sameo@rivosinc.com, shikemeng@huaweicloud.com, willy@infradead.org, vincent.chen@sifive.com, guoren@kernel.org, samitolvanen@google.com, songshuaishuai@tinylab.org, gerg@kernel.org, heiko@sntech.de, bhe@redhat.com, jeeheng.sia@starfivetech.com, cyy@cyyself.name, maskray@google.com, ancientmodern4@gmail.com, mathis.salmen@matsal.de, cuiyunhui@bytedance.com, bgray@linux.ibm.com, mpe@ellerman.id.au, baruch@tkos.co.il, alx@kernel.org, david@redhat.com, catalin.marinas@arm.com, revest@chromium.org, josh@joshtriplett.org, shr@devkernel.io, deller@gmx.de, omosnace@redhat.com, ojeda@kernel.org, jhubbard@nvidia.com Subject: Re: [PATCH v3 06/29] riscv: zicfiss / zicfilp extension csr and bit definitions Message-ID: References: <20240403234054.2020347-1-debug@rivosinc.com> <20240403234054.2020347-7-debug@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240403234054.2020347-7-debug@rivosinc.com> On Wed, Apr 03, 2024 at 04:34:54PM -0700, Deepak Gupta wrote: > zicfiss and zicfilp extension gets enabled via b3 and b2 in *envcfg CSR. > menvcfg controls enabling for S/HS mode. henvcfg control enabling for VS > while senvcfg controls enabling for U/VU mode. > > zicfilp extension extends *status CSR to hold `expected landing pad` bit. > A trap or interrupt can occur between an indirect jmp/call and target > instr. `expected landing pad` bit from CPU is recorded into xstatus CSR so > that when supervisor performs xret, `expected landing pad` state of CPU can > be restored. > > zicfiss adds one new CSR > - CSR_SSP: CSR_SSP contains current shadow stack pointer. > > Signed-off-by: Deepak Gupta > --- > arch/riscv/include/asm/csr.h | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > index bbd2207adb39..3bb126d1c5ff 100644 > --- a/arch/riscv/include/asm/csr.h > +++ b/arch/riscv/include/asm/csr.h > @@ -18,6 +18,15 @@ > #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ > #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ > > +/* zicfilp landing pad status bit */ > +#define SR_SPELP _AC(0x00800000, UL) > +#define SR_MPELP _AC(0x020000000000, UL) > +#ifdef CONFIG_RISCV_M_MODE > +#define SR_ELP SR_MPELP > +#else > +#define SR_ELP SR_SPELP > +#endif > + > #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ > #define SR_FS_OFF _AC(0x00000000, UL) > #define SR_FS_INITIAL _AC(0x00002000, UL) > @@ -196,6 +205,8 @@ > #define ENVCFG_PBMTE (_AC(1, ULL) << 62) > #define ENVCFG_CBZE (_AC(1, UL) << 7) > #define ENVCFG_CBCFE (_AC(1, UL) << 6) > +#define ENVCFG_LPE (_AC(1, UL) << 2) > +#define ENVCFG_SSE (_AC(1, UL) << 3) > #define ENVCFG_CBIE_SHIFT 4 > #define ENVCFG_CBIE (_AC(0x3, UL) << ENVCFG_CBIE_SHIFT) > #define ENVCFG_CBIE_ILL _AC(0x0, UL) > @@ -216,6 +227,11 @@ > #define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT) > #define SMSTATEEN0_SSTATEEN0_SHIFT 63 > #define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT) > +/* > + * zicfiss user mode csr > + * CSR_SSP holds current shadow stack pointer. > + */ > +#define CSR_SSP 0x011 > > /* symbolic CSR names: */ > #define CSR_CYCLE 0xc00 > -- > 2.43.2 > Reviewed-by: Charlie Jenkins