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From: Charlie Jenkins <charlie@rivosinc.com>
To: zhouquan@iscas.ac.cn
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-kselftest@vger.kernel.org, oleg@redhat.com,
	paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, andy.chiu@sifive.com, shuah@kernel.org
Subject: Re: [PATCH v1 1/2] riscv: Expose orig_a0 in the user_regs_struct structure
Date: Mon, 1 Jul 2024 21:34:16 -0700	[thread overview]
Message-ID: <ZoODSMYCRbNcZWaY@ghost> (raw)
In-Reply-To: <a424caf3072d12ef6ba0c56c411789fb3282e844.1719408040.git.zhouquan@iscas.ac.cn>

On Thu, Jun 27, 2024 at 11:02:46AM +0800, zhouquan@iscas.ac.cn wrote:
> From: Quan Zhou <zhouquan@iscas.ac.cn>
> 
> Expose orig_a0 to userspace to ensure that users can modify
> the actual value of `a0` in the traced process through the
> ptrace(PTRACE_SETREGSET, ...) path.
> 
> The addition of orig_a0 also requires the following adjustments:
> 1) Adjust the position of orig_a0 in pt_regs to ensure correct copying.
> 2) MAX_REG_OFFSET should match the new bottom of pt_regs.
> 
> Suggested-by: Charlie Jenkins <charlie@rivosinc.com>
> Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn>
> ---
>  arch/riscv/include/asm/ptrace.h      | 7 ++++---
>  arch/riscv/include/uapi/asm/ptrace.h | 2 ++
>  2 files changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/riscv/include/asm/ptrace.h b/arch/riscv/include/asm/ptrace.h
> index b5b0adcc85c1..380cf54c1f3d 100644
> --- a/arch/riscv/include/asm/ptrace.h
> +++ b/arch/riscv/include/asm/ptrace.h
> @@ -12,6 +12,7 @@
>  
>  #ifndef __ASSEMBLY__
>  
> +/* MAX_REG_OFFSET should match the bottom of pt_regs */
>  struct pt_regs {
>  	unsigned long epc;
>  	unsigned long ra;
> @@ -45,12 +46,12 @@ struct pt_regs {
>  	unsigned long t4;
>  	unsigned long t5;
>  	unsigned long t6;
> +	/* a0 value before the syscall */
> +	unsigned long orig_a0;
>  	/* Supervisor/Machine CSRs */
>  	unsigned long status;
>  	unsigned long badaddr;
>  	unsigned long cause;
> -	/* a0 value before the syscall */
> -	unsigned long orig_a0;
>  };
>  
>  #define PTRACE_SYSEMU			0x1f
> @@ -64,7 +65,7 @@ struct pt_regs {
>  
>  #define user_mode(regs) (((regs)->status & SR_PP) == 0)
>  
> -#define MAX_REG_OFFSET offsetof(struct pt_regs, orig_a0)
> +#define MAX_REG_OFFSET offsetof(struct pt_regs, cause)
>  
>  /* Helpers for working with the instruction pointer */
>  static inline unsigned long instruction_pointer(struct pt_regs *regs)
> diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h
> index a38268b19c3d..3e37f80cb3e8 100644
> --- a/arch/riscv/include/uapi/asm/ptrace.h
> +++ b/arch/riscv/include/uapi/asm/ptrace.h
> @@ -54,6 +54,8 @@ struct user_regs_struct {
>  	unsigned long t4;
>  	unsigned long t5;
>  	unsigned long t6;
> +	/* a0 value before the syscall */
> +	unsigned long orig_a0;
>  };
>  
>  struct __riscv_f_ext_state {
> -- 
> 2.34.1
> 

Thank you!

Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>


  reply	other threads:[~2024-07-02  4:34 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-27  3:02 [PATCH v1 0/2] riscv: Expose orig_a0 to userspace for ptrace to set the actual a0 zhouquan
2024-06-27  3:02 ` [PATCH v1 1/2] riscv: Expose orig_a0 in the user_regs_struct structure zhouquan
2024-07-02  4:34   ` Charlie Jenkins [this message]
2024-06-27  3:02 ` [PATCH v1 2/2] riscv: selftests: Add a ptrace test to verify syscall parameter modification zhouquan
2024-07-02  5:37   ` Charlie Jenkins

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