From: Aoba K <nExp_0x17@outlook.com>
To: "charlie@rivosinc.com" <charlie@rivosinc.com>
Cc: "ajones@ventanamicro.com" <ajones@ventanamicro.com>,
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Subject: Re: [PATCH v10 00/14] riscv: Add support for xtheadvector
Date: Sun, 29 Sep 2024 12:44:07 +0000 [thread overview]
Message-ID: <a1f41f92-6bd0-48b6-a931-e7ad7aba18cc@outlook.com> (raw)
In-Reply-To: <20240911-xtheadvector-v10-0-8d3930091246@rivosinc.com>
Hello Charlie,
I've been working on bringing up the Sipeed Lichee RV Dock
(which also uses the D1 SoC) with the kernel patches you provided.
The patches applied cleanly to Palmer's for-next branch,
but I've encountered a couple of issues:
1. Skiffos Compilation Error during the compilation process of `cgo`:
`unknown relocation type 17; compiled without -fpic?`
Unfortunately, I closed the terminal before saving the full log,
so I don't have the complete details, but the result should be reproducible.
While this should be a SkiffOS issue, mention it in case SkiffOS is the method
that you mentioned for bringing up the device.
2. Image Building with sehraf/riscv-arch-image-builder:
After building the image, the device failed to start at an early stage.
I suspect this may be related to incorrect RAM size detection,
as the board only has 512MB of RAM.
Interestingly, the vendor image reports 1GB, and the Sipeed website also states
that the Dock has 1GB, despite there being no extra memory bank present.
You can find the boot log here: https://fars.ee/bdYk.log
Any help would be appreciated, and big thanks to your work
to make the efficient part of this board to work (again)!
Cheers,
Aoba
next prev parent reply other threads:[~2024-09-29 12:44 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-12 5:55 [PATCH v10 00/14] riscv: Add support for xtheadvector Charlie Jenkins
2024-09-12 5:55 ` [PATCH v10 01/14] dt-bindings: riscv: Add xtheadvector ISA extension description Charlie Jenkins
2024-10-02 15:07 ` Andy Chiu
2024-09-12 5:55 ` [PATCH v10 02/14] dt-bindings: cpus: add a thead vlen register length property Charlie Jenkins
2024-10-02 16:05 ` Andy Chiu
2024-09-12 5:55 ` [PATCH v10 03/14] riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree Charlie Jenkins
2024-11-12 2:12 ` D1 vlenb h1k0n
2024-11-12 18:03 ` Conor Dooley
2024-09-12 5:55 ` [PATCH v10 04/14] riscv: Add thead and xtheadvector as a vendor extension Charlie Jenkins
2024-09-12 5:55 ` [PATCH v10 05/14] riscv: vector: Use vlenb from DT for thead Charlie Jenkins
2024-10-02 16:34 ` Andy Chiu
2024-11-09 19:34 ` Yangyu Chen
2024-11-14 2:24 ` Charlie Jenkins
2024-09-12 5:55 ` [PATCH v10 06/14] RISC-V: define the elements of the VCSR vector CSR Charlie Jenkins
2024-10-06 16:04 ` Andy Chiu
2024-09-12 5:55 ` [PATCH v10 07/14] riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT Charlie Jenkins
2024-10-06 16:11 ` Andy Chiu
2024-09-12 5:55 ` [PATCH v10 08/14] riscv: Add xtheadvector instruction definitions Charlie Jenkins
2024-09-12 5:55 ` [PATCH v10 09/14] riscv: vector: Support xtheadvector save/restore Charlie Jenkins
2024-10-08 17:34 ` Andy Chiu
2024-09-12 5:55 ` [PATCH v10 10/14] riscv: hwprobe: Add thead vendor extension probing Charlie Jenkins
2024-10-02 16:59 ` Emil Renner Berthing
2024-10-29 18:00 ` Yangyu Chen
2024-09-12 5:55 ` [PATCH v10 11/14] riscv: hwprobe: Document thead vendor extensions and xtheadvector extension Charlie Jenkins
2024-09-12 5:55 ` [PATCH v10 12/14] selftests: riscv: Fix vector tests Charlie Jenkins
2024-09-12 5:55 ` [PATCH v10 13/14] selftests: riscv: Support xtheadvector in " Charlie Jenkins
2024-09-12 5:55 ` [PATCH v10 14/14] riscv: Add ghostwrite vulnerability Charlie Jenkins
2024-09-16 17:12 ` Conor Dooley
2024-09-16 18:44 ` Charlie Jenkins
2024-09-16 18:56 ` Conor Dooley
2024-09-29 12:44 ` Aoba K [this message]
2024-09-30 14:53 ` [PATCH v10 00/14] riscv: Add support for xtheadvector Conor Dooley
2024-09-30 15:50 ` 回覆: " Aoba K
2024-09-29 16:07 ` Aoba K
2024-11-14 2:44 ` Charlie Jenkins
2025-01-21 14:19 ` nexp_0x17
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