From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B37E222B8B9; Wed, 21 May 2025 20:01:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747857714; cv=none; b=TtJQ25Vzy4pQu5/ni+I9HAu9Jq1V+2in4IRlgzjaGua1MvfhT++bBid3W8tMwOZp4yizPwK7E2RG4APYGPOe3/CM4VbOsY/byFexkOykaoSlyh9dANNYxYhlcGZTLBRCptCdUmwmeb4zpSw09bKNvAlOiT8i4R3L1oYxG5P8ESI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747857714; c=relaxed/simple; bh=8oYbHgi3dSN5sYtlh/M8hB45JGShP32FfZWXEuCKwsE=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=WpufVu42eo/L/1ceLHwBzvqPKkgKQ+ipgFsy7gopQT7UEqFCtabKtkpLV3ZZgMxnmphlkQWGED96xvZ0IEdnhvUPOWzm5bK25W6GeFaTbEIJab4qty+3/IPnOfCSlyIF1iQQy79dmmkNubjgKg1WIocurrbdmQivpR06TwM9sI8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qHwsJb1g; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qHwsJb1g" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B6E29C4CEE4; Wed, 21 May 2025 20:01:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747857714; bh=8oYbHgi3dSN5sYtlh/M8hB45JGShP32FfZWXEuCKwsE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=qHwsJb1guGYXx1+pNKHsKaypiXjembrKX2sSgoSJ0j7QCGEEdPPUWbBntdksMO/SU fNkU7WW01z68lrC57WN7qyTKJPc/XT4rOUHUi91E541kElQdob7QADDDTjxxCJWFV6 Wf68LGqXGj9AfTH9UnvpbwRgoxMnazzv5OYjTPnvkje4QZ3hfviKHfAkR6XMuXy0/B lmA0ikIcLg9UfQlnGciH4+5dSLQVAN0WAQUXv1z9XQYzFCoAYBDWVFcfWM/ZWO4Nz0 god95dJdtAkDsSJFcODryRQajeFr2LwhRB4l72jkRSbzXx3xv+z+m/5Ygba584mf9k HqhLf0FEC5Ewg== Date: Wed, 21 May 2025 13:01:52 -0700 From: Namhyung Kim To: Mingwei Zhang Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Sean Christopherson , Paolo Bonzini , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Liang@google.com, Kan , "H. Peter Anvin" , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, Yongwei Ma , Xiong Zhang , Dapeng Mi , Jim Mattson , Sandipan Das , Zide Chen , Eranian Stephane , Shukla Manali , Nikunj Dadhania Subject: Re: [PATCH v4 09/38] perf: Add switch_guest_ctx() interface Message-ID: References: <20250324173121.1275209-1-mizhang@google.com> <20250324173121.1275209-10-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20250324173121.1275209-10-mizhang@google.com> On Mon, Mar 24, 2025 at 05:30:49PM +0000, Mingwei Zhang wrote: > From: Kan Liang > > When entering/exiting a guest, some contexts for a guest have to be > switched. For examples, there is a dedicated interrupt vector for > guests on Intel platforms. > > When PMI switch into a new guest vector, guest_lvtpc value need to be > reflected onto HW, e,g., guest clear PMI mask bit, the HW PMI mask > bit should be cleared also, then PMI can be generated continuously > for guest. So guest_lvtpc parameter is added into perf_guest_enter() > and switch_guest_ctx(). > > Add a dedicated list to track all the pmus with the PASSTHROUGH cap, which s/PASSTHROUGH/MEDIATED_VPMU/ ? Thanks, Namhyung > may require switching the guest context. It can avoid going through the > huge pmus list. > > Suggested-by: Peter Zijlstra (Intel) > Signed-off-by: Kan Liang > Signed-off-by: Mingwei Zhang