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Thu, 15 May 2025 19:30:30 -0700 Date: Thu, 15 May 2025 19:30:29 -0700 From: Nicolin Chen To: "Tian, Kevin" CC: "jgg@nvidia.com" , "corbet@lwn.net" , "will@kernel.org" , "bagasdotme@gmail.com" , "robin.murphy@arm.com" , "joro@8bytes.org" , "thierry.reding@gmail.com" , "vdumpa@nvidia.com" , "jonathanh@nvidia.com" , "shuah@kernel.org" , "jsnitsel@redhat.com" , "nathan@kernel.org" , "peterz@infradead.org" , "Liu, Yi L" , "mshavit@google.com" , "praan@google.com" , "zhangzekun11@huawei.com" , "iommu@lists.linux.dev" , "linux-doc@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-tegra@vger.kernel.org" , "linux-kselftest@vger.kernel.org" , "patches@lists.linux.dev" , "mochs@nvidia.com" , "alok.a.tiwari@oracle.com" , "vasant.hegde@amd.com" Subject: Re: [PATCH v4 10/23] iommufd/viommu: Introduce IOMMUFD_OBJ_HW_QUEUE and its related struct Message-ID: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2025 02:30:47.7012 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 85501780-4a43-412f-93f5-08dd9421aae6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003445.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8451 On Thu, May 15, 2025 at 05:58:41AM +0000, Tian, Kevin wrote: > > From: Nicolin Chen > > Sent: Friday, May 9, 2025 11:03 AM > > > > Add IOMMUFD_OBJ_HW_QUEUE with an iommufd_hw_queue structure, > > representing > > a HW-accelerated queue type of IOMMU's physical queue that can be passed > > through to a user space VM for direct hardware control, such as: > > - NVIDIA's Virtual Command Queue > > - AMD vIOMMU's Command Buffer, Event Log Buffer, and PPR Log Buffer > > > > Introduce an allocator iommufd_hw_queue_alloc(). And add a pair of > > viommu > > ops for iommufd to forward user space ioctls to IOMMU drivers. > > > > Given that the first user of this HW QUEUE (tegra241-cmdqv) will need to > > ensure the queue memory to be physically contiguous, add a flag property > > in iommufd_viommu_ops and > > IOMMUFD_VIOMMU_FLAG_HW_QUEUE_READS_PA to allow > > driver to flag it so that the core will validate the physical pages of a > > given guest queue. > > 'READS' is confusing here. What about xxx_CONTIG_PAS? Combining Jason's first comments here: https://lore.kernel.org/linux-iommu/20250515160620.GJ382960@nvidia.com/ So, pinning should be optional too. And I think there would be unlikely a case where HW needs contiguous physical pages while not requiring to pin the pages, right? So, we need an flag that could indicate to do both tests. Yet, "xxx_CONTIG_PAS" doesn't sound very fitting, compared to this "IOMMUFD_VIOMMU_FLAG_HW_QUEUE_READS_PA". Perhaps, we should just add some comments to clarify a bit. Or do you have some better naming? Thanks Nicolin