From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-180.mta1.migadu.com (out-180.mta1.migadu.com [95.215.58.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 038624A23; Sat, 21 Jun 2025 00:44:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.180 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750466674; cv=none; b=qmTGvo6szhTE5YRmkDdmfCTGfKgmf91Zdd10OCwIvFWQpZ9FHWAPHmKxw4vXbdEExhJ/rrCQJ3Dceh8OubIDT2od0saiS+8A+TaTV+dSMCLpQdB0Xh7C161FaBWwTNOu1O4foUhjedXOT3kTIkjVqDFkrR6+VB1+WuHnjNHU9PM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750466674; c=relaxed/simple; bh=gO8cC4rKWEJXRxytJil89DYZW1Zo5HvSggak9PiMV6s=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=NKze7Elvg4FK88AdhOo7FBxRuVenB+/vLpYZBXPQGSdSiLgsQVgr8cQeLpzBYKkOVvZhXgYjy/OByK66QpkA1g3qn9gppJUCWXScnIHAmkc/PeN4q+gT2oospoSt81HOmnIXbkzHYFDQj4cJuRr33MRVWh6KxxV49QPCa46JTwA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=UZ/5ECnu; arc=none smtp.client-ip=95.215.58.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="UZ/5ECnu" Date: Fri, 20 Jun 2025 17:44:14 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1750466669; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=yCQ8zfuNYckMQwi0qvUEsR7Le3lMOKXcVy5xk0DxTYA=; b=UZ/5ECnuGxQxLGkdlEVk5aN863gG4arF7YO8/7tQT2PR15Yom3lU3nhRIGghO8pVgcTkKp TKcxke9ArrcHNI70a7paWMs4pBKKKrKAbEQDXIak/UGnQARCQoas/eaBbznjs45wzybj7J f7oqDRxJ5PeJ0wwRzxTWPQ1SYlxg0V8= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Colton Lewis Cc: kvm@vger.kernel.org, Paolo Bonzini , Jonathan Corbet , Russell King , Catalin Marinas , Will Deacon , Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Mark Rutland , Shuah Khan , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH v2 01/23] arm64: cpufeature: Add cpucap for HPMN0 Message-ID: References: <20250620221326.1261128-1-coltonlewis@google.com> <20250620221326.1261128-2-coltonlewis@google.com> Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250620221326.1261128-2-coltonlewis@google.com> X-Migadu-Flow: FLOW_OUT On Fri, Jun 20, 2025 at 10:13:01PM +0000, Colton Lewis wrote: > Add a capability for FEAT_HPMN0, whether MDCR_EL2.HPMN can specify 0 > counters reserved for the guest. > > This required changing HPMN0 to an UnsignedEnum in tools/sysreg > because otherwise not all the appropriate macros are generated to add > it to arm64_cpu_capabilities_arm64_features. > > Signed-off-by: Colton Lewis > --- > arch/arm64/kernel/cpufeature.c | 8 ++++++++ > arch/arm64/tools/cpucaps | 1 + > arch/arm64/tools/sysreg | 6 +++--- > 3 files changed, 12 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index b34044e20128..278294fdc97d 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -548,6 +548,7 @@ static const struct arm64_ftr_bits ftr_id_mmfr0[] = { > }; > > static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_HPMN0_SHIFT, 4, 0), > S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), > @@ -2896,6 +2897,13 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .matches = has_cpuid_feature, > ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, FGT2) > }, > + { > + .desc = "Allow MDCR_EL2.HPMN = 0", This feedback still stands... .desc = "HPMN0", [*] https://lore.kernel.org/kvm/aD4ijUaSGm9b2g5H@linux.dev/ > + .type = ARM64_CPUCAP_SYSTEM_FEATURE, > + .capability = ARM64_HAS_HPMN0, > + .matches = has_cpuid_feature, > + ARM64_CPUID_FIELDS(ID_AA64DFR0_EL1, HPMN0, IMP) > + }, > #ifdef CONFIG_ARM64_SME > { > .desc = "Scalable Matrix Extension", > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index 10effd4cff6b..5b196ba21629 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -39,6 +39,7 @@ HAS_GIC_CPUIF_SYSREGS > HAS_GIC_PRIO_MASKING > HAS_GIC_PRIO_RELAXED_SYNC > HAS_HCR_NV1 > +HAS_HPMN0 > HAS_HCX > HAS_LDAPR > HAS_LPA2 > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index 8a8cf6874298..d29742481754 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -1531,9 +1531,9 @@ EndEnum > EndSysreg > > Sysreg ID_AA64DFR0_EL1 3 0 0 5 0 > -Enum 63:60 HPMN0 > - 0b0000 UNPREDICTABLE > - 0b0001 DEF > +UnsignedEnum 63:60 HPMN0 > + 0b0000 NI > + 0b0001 IMP > EndEnum > UnsignedEnum 59:56 ExtTrcBuff > 0b0000 NI > -- > 2.50.0.714.g196bf9f422-goog >