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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2026 09:33:39.2778 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4c99c2ab-ae8a-41cf-ba2b-08de5806fe5b X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF0000A798.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV2PR08MB11280 Hi, > Hi Will, > > > On Mon, Dec 15, 2025 at 09:56:04AM +0000, Yeoreum Yun wrote: > > > Hi, > > > > > > > On Sun, 14 Dec 2025 11:22:48 +0000, > > > > Yeoreum Yun wrote: > > > > > > > > > > Apply the FEAT_LSUI instruction to emulate the deprecated swpX > > > > > instruction, so that toggling of the PSTATE.PAN bit can be removed when > > > > > LSUI-related instructions are used. > > > > > > > > > > Signed-off-by: Yeoreum Yun > > > > > > > > It really begs the question: what are the odds of ever seeing a CPU > > > > that implements both LSUI and AArch32? > > > > > > > > This seems extremely unlikely to me. > > > > > > Well, I'm not sure how many CPU will have > > > both ID_AA64PFR0_EL1.EL0 bit as 0b0010 and FEAT_LSUI > > > (except FVP currently) -- at least the CPU what I saw, > > > most of them set ID_AA64PFR0_EL1.EL0 as 0b0010. > > > > Just to make sure I understand you, you're saying that you have seen > > a real CPU that implements both 32-bit EL0 *and* FEAT_LSUI? > > > > > If you this seems useless, I don't have any strong comments > > > whether drop patches related to deprecated swp instruction parts > > > (patch 8-9 only) or not. > > > (But, I hope to pass this decision to maintaining perspective...) > > > > I think it depends on whether or not the hardware exists. Marc thinks > > that it's extremely unlikely whereas you appear to have seen some (but > > please confirm). > > > > What I meant was not a 32-bit CPU with LSUI, but a CPU that supports > 32-bit EL0 compatibility (i.e. ID_AA64PFR0_EL1.EL0 = 0b0010). > My point was that if CPUs implementing LSUI do appear, most of them will likely > continue to support the existing 32-bit EL0 compatibility that > the majority of current CPUs already have. > > For that reason, I think it also makes sense to apply LSUI to SWPx emulation. > That said, since there are currently no real CPUs that actually implement LSUI, > it is hard to say that this is particularly useful right now. > I do not have a strong opinion on whether this patch should be applied or > dropped at this point. > Personally, given that most CPUs released so far support 32-bit compatibility, > I expect that future CPUs with LSUI will also retain 32-bit compatibility. > However, it is difficult to say with certainty which approach > is correct at this time. > > I would therefore like to defer the final decision on this to the maintainers > > Am I missing something? Ah, the Marc view was right. So I think the changes for swpX could be droppable. Thanks. -- Sincerely, Yeoreum Yun